SSTVF16859 datasheet(9/15 Pages) PHILIPS

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Philips Semiconductors

Product data sheet

SSTVF16859

13-bit 1:2 SSTL_2 registered buffer for DDR

2004 Jul 12

TIMING REQUIREMENTS—PC1600–PC2700

Over recommended operating conditions; Tamb = 0 °C to +70 °C (unless otherwise noted) (see Figure 1)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

VDD = 2.5 V ± 0.2 V

UNIT

MIN

MAX

fclock

Clock frequency

—

200

MHz

Pulse duration, CK, CK HIGH or LOW

2.5

—

tact

Differential inputs active time

Notes 1, 2

—

tinact

Differential inputs inactive time

Notes 1, 3

—

Setup time, fast slew rate

(see Notes 4 and 6)

Data before CK

↑ CK↓

0.65

tsu

Setup time, slow slew rate

(see Notes 5 and 6)

Data before CK

↑, CK↓

0.75

Hold time, fast slew rate

(see Notes 4 and 6)

Data after CK

↑ CK↓

0.75

Hold time, slow slew rate

(see Notes 5 and 6)

Data after CK

↑, CK↓

0.9

NOTES:

1. This parameter is not necessarily production tested.

2. Data inputs must be below a minimum time of tact max, after RESET is taken HIGH.

3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW.

4. For data signal input slew rate

≥ 1 V/ns.

5. For data signal input slew rate

≥ 0.5 V/ns and < 1 V/ns.

6. CK, CK signals input slew rates are

≥ 1 V/ns.

TIMING REQUIREMENTS—PC3200

Over recommended operating conditions; Tamb = 0 °C to +70 °C (unless otherwise noted) (see Figure 1)

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

VDD = 2.6 V ± 0.1 V

UNIT

MIN

MAX

fclock

Clock frequency

—

210

MHz

Pulse duration, CK, CK HIGH or LOW

2.5

—

tact

Differential inputs active time

Notes 1, 2

—

tinact

Differential inputs inactive time

Notes 1, 3

—

Setup time, fast slew rate

(see Notes 4 and 6)

Data before CK

↑ CK↓

0.65

tsu

Setup time, slow slew rate

(see Notes 5 and 6)

Data before CK

↑, CK↓

0.75

Hold time, fast slew rate

(see Notes 4 and 6)

Data after CK

↑ CK↓

0.65

Hold time, slow slew rate

(see Notes 5 and 6)

Data after CK

↑, CK↓

0.8

NOTES:

1. This parameter is not necessarily production tested.

2. Data inputs must be below a minimum time of tact max, after RESET is taken HIGH.

3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken LOW.

4. For data signal input slew rate

≥ 1 V/ns.

5. For data signal input slew rate

≥ 0.5 V/ns and < 1 V/ns.

6. CK, CK signals input slew rates are

≥ 1 V/ns.

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