LPC2888 datasheet(15/34 Pages) PHILIPS

15 / 34 page

LPC2880_LPC2888_1

Preliminary data sheet

Rev. 01 — 22 June 2006

15 of 34

Philips Semiconductors

LPC2880; LPC2888

16/32-bit ARM microcontrollers with external memory interface

6.3 Cache

The CPU of the LPC2880/LPC2888 has been extended with a 2-way set-associative

cache controller. The cache is 8 kB in size and can store both data and instruction code.

If code that is being executed is present in the cache from a previous execution, the CPU

will not experience code fetch waits. Similarly, if requested data is present in the cache,

the CPU will not experience a data access wait.

The trade-off of introducing this cache is that each AHB access that bypasses the cache

will have an extra wait state inserted. Therefore it is advisable to enable instruction

caching (and preferably data caching as well) for all memories, to provide the highest

performance.

6.3.1 Cache operation

This cache works as follows, for each page of which the cache is enabled:

• If a read is requested and the information is not in the cache (a cache miss), a line of

eight 32-bit words will be read from the AHB bus. The CPU waits until this process is

complete.

• If a read is requested and the information is found in the cache (a cache hit), the

information is read from cache, with zero wait states.

• If data is written, and the location is not in the cache (a cache miss), the data will be

written directly to memory.

• If data is written, and the location is in the cache, because this location has been read

before (a cache hit), then data is written into the cache with zero wait states and the

cache line is marked as ‘dirty’.

• If a ‘dirty’ cache line is about to be discarded because of a cache miss on a read

request, this line will ﬁrst be written back to memory (a cache-line ﬂush).

The cache can be set to data-only, instruction-only or combined (uniﬁed) caching. The

cache has 16 conﬁgurable pages, each 2 MB in range. The pages occupy the bottom

32 MB of the memory map. The virtual address and enable/disable status is conﬁgurable

for each page.

6.3.2 Features

• 8 kB, 2-way set-associative cache.

• May be used as both an instruction and data cache.

• Zero wait states for a cache hit.

• 16 conﬁgurable pages, each 2 MB in range.

6.4 Flash memory and programming

The LPC2888 incorporates 1 MB ﬂash memory system, while the LPC2880 is a ﬂash-less

device. The ﬂash memory of the LPC2888 may be used for both code and data storage.

Programming of the ﬂash memory may be accomplished in several ways. It may be

programmed In System via the USB port. The application program may also erase and/or

program the ﬂash while the application is running, allowing a great degree of ﬂexibility for

data storage, ﬁeld ﬁrmware upgrades, etc.

LPC2888 bảng dữ liệu(PDF) 15 Page - NXP Semiconductors

LPC2888 bảng dữ liệu(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

bảng dữ liệu tải về

Link URL