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MCP2030 bảng dữ liệu(PDF) 32 Page - Microchip Technology |
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MCP2030 bảng dữ liệu(HTML) 32 Page - Microchip Technology |
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32 / 66 page ![]() MCP2030 DS21981A-page 32 © 2005 Microchip Technology Inc. 5.7 Fixed Gain Amplifiers 1 and 2 FGA1 and FGA2 provides a maximum two-stage gain of 40 dB. 5.8 Auto-Channel Selection The auto-channel selection feature is enabled if the Auto-Channel Select bit AUTOCHSEL<8> in Configu- ration Register 5 (Register 5-6) is set, and disabled if the bit is cleared. When this feature is active (i.e., AUTOCHSE <8> = 1), the control circuit checks the demodulator output of each input channel immediately after the AGC settling time (TSTAB). If the output is high, it allows this channel to pass data, otherwise it is blocked. The status of this operation is monitored by STATUS Register 7 bits <8:6> (Register 5-8). These bits indicate the current status of the channel selection activity, and automatically updates for every Soft Reset period. The auto-channel selection function resets after each Soft Reset (or after Inactivity timer time-out). Therefore, the blocked channels are re-enabled after Soft Reset. This feature can make the output signal cleaner by blocking any channel that was not high at the end of TAGC. This function works only for demodulated data output, and is not applied for carrier clock or RSSI output. 5.9 Carrier Clock Detector The Carrier Clock Detector senses the input carrier cycles. The output of the detector switches digitally at the signal carrier frequency. Carrier clock output is available when the output is selected by the DATOUT bit in Configuration Register 1 (Register 5-2). 5.10 Demodulator The Demodulator consists of a full-wave rectifier, low pass filter, peak detector and Data Slicer that detects the envelope of the input signal. 5.11 Data Slicer The Data Slicer consists of a reference generator and comparator. The Data Slicer compares the input with the reference voltage. The reference voltage comes from the minimum modulation depth requirement setting and input peak voltage. The data from all 3 channels are OR’d together and sent to the output enable filter. 5.12 Output Enable Filter The Output Enable Filter enables the LFDATA output once the incoming signal meets the wake-up sequence requirements (see Section 5.15 “Configurable Output Enable Filter”). 5.13 Received Signal Strength Indicator (RSSI) The RSSI provides a current which is proportional to the input signal amplitude (see Section 5.30.3 “Received Signal Strength Indicator (RSSI) Output”). 5.14 Analog Front-End Timers The device has an internal 32 kHz RC oscillator. The oscillator is used in several timers: • Inactivity timer • Alarm timer •Pulse width timer • Period timer • AGC settling timer 5.14.1 RC OSCILLATOR The RC oscillator generates a 32 kHz internal clock. Note: The user cannot control the gain of these two amplifiers. |
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