IP175DLF datasheet(2/145 Pages) ETC

2 / 145 page

IP175DLF

Datasheet

2/145

August 22, 2014

IP175DLF-DS-R10.1

Table of Contents

Features................................................................................................................................................... 1

General Description ................................................................................................................................. 1

Table of Contents ..................................................................................................................................... 2

Revision History ....................................................................................................................................... 5

Disclaimer ................................................................................................................................................ 6

Feature comparison between IP175C and IP175DLF............................................................................. 7

Pin Diagram .................................................................................................................................... 9

Pin Description .............................................................................................................................. 13

Function Description ..................................................................................................................... 37

3.1

Flow Control ....................................................................................................................... 37

3.2

Broadcast Storm Protection ............................................................................................... 37

3.3

Rate Control ....................................................................................................................... 37

3.4

External MII ........................................................................................................................ 39

3.4.1

To define the speed, duplex and pause of MII port ............................................... 40

3.4.2

The Application Circuit of RMII.............................................................................. 43

3.5

Virtual LAN (VLAN) ............................................................................................................ 45

3.5.1

Port-based VLAN .................................................................................................. 45

3.5.2

Tag-based VLAN ................................................................................................... 45

3.5.3

VLAN Ingress Filtering .......................................................................................... 45

3.5.4

Shared and Independent VLAN Learning ............................................................. 45

3.5.5

The determination of the requirement to insert or remove tag.............................. 45

3.6

Quality of Service (QoS) .................................................................................................... 46

3.6.1

Traffic Policy.......................................................................................................... 46

3.6.2

Priority Classification............................................................................................. 46

3.6.3

Output Queue Scheduling..................................................................................... 48

3.7

Port mirror .......................................................................................................................... 48

3.8

Layer 2-4 Multi-Field Classification .................................................................................... 48

3.9

MAC Address Table............................................................................................................ 48

3.9.1

Entry Content ........................................................................................................ 49

3.9.2

Accessing MAC Table ........................................................................................... 51

3.10

CPU Interrupt Control for loop detection (for v13 or newer version).................................. 52

3.11

IGMP Snooping .................................................................................................................. 52

3.12

Security Filtering................................................................................................................. 52

3.12.1

Physical Port Filtering ........................................................................................... 52

3.12.2

MAC Address Filtering .......................................................................................... 52

3.12.3

Logical Port Filtering ............................................................................................. 52

3.12.4

Layer 2-4 Multi-Field Filtering................................................................................ 53

3.13

IEEE 802.1x ....................................................................................................................... 53

3.14

Spanning Tree .................................................................................................................... 53

3.15

Special Tag ......................................................................................................................... 53

3.16

Loop Detection ................................................................................................................... 55

3.17

Serial Mode LED ................................................................................................................ 55

3.18

LED Blink Timing ................................................................................................................ 57

3.19

Serial Management Interface ............................................................................................. 58

3.20

Reset .................................................................................................................................. 59

3.21

Built in regulator ................................................................................................................. 59

PHY Register ................................................................................................................................59

4.1

PHY ID Map ....................................................................................................................... 59

4.2

PHY 0~5 Register Map ...................................................................................................... 60

4.3

MII Register 0 ..................................................................................................................... 61

4.3.1

MII Register 0 of PHY0~4 ..................................................................................... 61

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