Rev. 1.4/ Oct. 2015

26

Input/Output Capacitance

Parameter

Symbol

DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866

Units Notes

Min

Max

Min

Max

Min

Max

Min

Max

Input/output capacitance

(DQ, DM, DQS, DQS,

TDQS, TDQS)

CIO

1.5

2.7

1.5

2.5

1.5

2.3

1.4

2.2

pF

1,2,3

Input capacitance, CK and

CK

CCK

0.8

1.6

0.8

1.4

0.8

1.4

0.8

1.3

pF

2,3

Input capacitance delta

CK and CK

CDCK

0

0.15

0

0.15

0

0.15

0

0.15

pF

2,3,4

Input capacitance delta,

DQS and DQS

CDDQS

0

0.20

0

0.15

0

0.15

0

0.15

pF

2,3,5

Input capacitance

(All other input-only pins)

CI

0.75

1.35

0.75

1.3

0.75

1.3

0.75

1.2

pF

2,3,6

Input capacitance delta

(All CTRL input-only pins)

CDI_CTRL -0.5

0.3

-0.4

0.2

-0.4

0.2

-0.4

0.2

pF

2,3,7,8

Input capacitance delta

(All ADD/CMD input-only

pins)

CDI_ADD_

CMD

-0.5

0.5

-0.4

0.4

-0.4

0.4

-0.4

0.4

pF

2,3,9,10

Input/output capacitance

delta

(DQ, DM, DQS, DQS)

CDIO

-0.5

0.3

-0.5

0.3

-0.5

0.3

-0.5

0.3

pF

2,3,11

Input/output capacitance

of ZQ pin

CZQ

-

3

-

3

-

3

-

3

pF

2,3,12

Notes:

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS.

2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is

measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NET-

WORK

ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,

RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK.

5. Absolute value of CIO(DQS)-CIO(DQS).

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTR applies to ODT, CS and CKE.

8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE.

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance an ZQ pin: 5 pF.