AD5764

Preliminary Technical Data

Rev. PrC 21-Oct-04| Page 22 of 28

OFFSET REGISTER

The Offset Register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 7). The Offset Register is an 8-bit register and allows the user to adjust the offset of each channel

by – 15.875 LSBs to + 16 LSBs in steps of 1/8 LSB as shown in Table 15 and Table 16.

Table 15. Programming the Offset Register

REG2

REG1

REG0

A2

A1

A0

D15 …. D8

D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

DAC Address

Don’t Care

OF7

OF6

OF5

OF4

OF3

OF2

OF1

OF0

Table 16. Offset Register options

Offset Adjustment

OF7

OF6

OF5

OF4

OF3

OF2

OF1

OF0

+15.875 LSBs

0

0

0

0

0

0

0

0

+15.75 LSBs

0

0

0

0

0

0

0

1

-

-

-

-

-

-

-

-

No Adjustment

1

0

0

0

0

0

0

0

-

-

-

-

-

-

-

-

-15.875 LSBs

1

1

1

1

1

1

1

0

-16 LSBs

1

1

1

1

1

1

1

1