74HC4040 datasheet(15/24 Pages) PHILIPS

15 / 24 page

74HC_HCT4040_3

Product data sheet

Rev. 03 — 14 September 2005

15 of 24

Philips Semiconductors

74HC4040; 74HCT4040

12-stage binary ripple counter

[1]

CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi + ∑(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

∑(C

L × VCC

× f

o) = sum of outputs;

CL = output load capacitance in pF;

VCC = supply voltage in V.

13. Waveforms

tPHL

propagation delay MR to Qn

VCC = 4.5 V; CL =50pF;

see Figure 8

--68

tTHL, tTLH

output transition time

VCC = 4.5 V; CL =50pF;

see Figure 8

--22

clock pulse width HIGH or LOW

VCC = 4.5 V; CL =50pF;

see Figure 8

master reset pulse width; HIGH

VCC = 4.5 V; CL =50pF;

see Figure 8

trec

recovery time MR to CP

VCC = 4.5 V; CL =50pF;

see Figure 8

fmax

maximum operating frequency

VCC = 4.5 V; CL =50pF;

see Figure 8

MHz

Table 10:

Dynamic characteristics for type 74HCT4040 …continued

GND = 0 V; tr = tf = 6 ns. For test circuit see Figure 9.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

74HC4040: VM = 50 %; VI = GND to VCC.

74HCT4040: VM = 1.3 V; VI = GND to 3 V.

Fig 8.

Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition

times, maximum clock pulse frequency, master reset (MR) pulse width, master

reset to output (Qn) propagation delays and master reset to clock (CP) removal

time.

MR input

CP input

Q0 or Qn

output

tPHL

1/fmax

trem

001aad590

tPLH

tTLH

tTHL

tPHL

74HC4040 bảng dữ liệu(PDF) 15 Page - NXP Semiconductors

74HC4040 bảng dữ liệu(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL