Figure 8-14. Output Voltage Ripple, 800 kHz FCCM,

35 A Load, PVIN = 12 V, VOUT = 3.3 V

Figure 8-15. Output Voltage Ripple, 800 kHz FCCM,

No load, PVIN = 12 V, VOUT = 3.3 V

Figure 8-16. Output Voltage Ripple, DCM, No load, PVIN = 12 V, VOUT = 3.3 V

8.3 Power Supply Recommendations

The device is designed to operate from a wide input voltage supply range between 2.7 V and 16 V when the

VDRV pin is powered by an external bias ranging from 4.75 V to 5.3 V. Both input supplies (PVIN and VDRV

bias) must be well regulated. Proper bypassing of input supplies (PVIN and VDRV) is also critical for noise

performance, as are PCB layout and grounding scheme. See the recommendations in Layout Guidelines.

8.4 Layout

8.4.1 Layout Guidelines

Layout is critical for good power supply design. Layout example shows the recommended PCB layout

configuration. A list of PCB layout considerations using the device is listed as follows:

• Place the power components (including input and output capacitors, the inductor, and the IC) on the top side

of the PCB. To shield and isolate the small signal traces from noisy power lines, insert at least one solid

ground inner plane.

• PVIN-to-PGND decoupling capacitors are important for FET robustness. Besides the large volume 0603 or

0805 ceramic capacitors, TI highly recommends a 0.1-µF, 0402 ceramic capacitor with 25-V / X7R rating on

PVIN pin 20 (top layer) to bypass any high frequency current in PVIN to PGND loop. TI recommends the

25-V rating, but can be lowered to 16-V rating for an application with tightly regulated 12-V input bus.

• When one or more PVIN-to-PGND decoupling capacitors are placed on bottom layer, extra impedance is

introduced to bypass IC PVIN node to IC PGND node. Placing at least 3 times PVIN vias on PVIN pad

TPS548C26

SLVSGM2 – MARCH 2023

www.ti.com

26

Submit Document Feedback

Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS548C26