AD9779PCB datasheet(18/34 Pages) AD

18 / 34 page

AD9779

Preliminary Technical Data

Rev. PrD | Page 18 of 34

Aux DAC1 Sign

0: Positive

1: Negative

Aux DAC1

Direction

0: Source

1: Sink

Aux DAC1 Sleep

0: Aux DAC1 on

1: Aux DAC 1 off

Auxiliary DAC1

Control and Data

1:0

Aux DAC1 Gain

Adjustment

(9:8) MSB slice of 10 bit gain setting word for Aux DAC1

QDAC Gain

7:0

QDAC Gain

Adjustment

(7:0) LSB slice of 10 bit gain setting word for QDAC

11111001

QDAC Sleep

0: QDAC on

1: QDAC off

QDAC Power

Down

0: QDAC on

1: QDAC off

QDAC Gain and

Control

1:0

QDAC Gain

Adjustment

(9:8) MSB slice of 10 bit gain setting word for QDAC

Auxiliary DAC2 Gain

7:0

Aux DAC2 Gain

Adjustment

(7:0) LSB slice of 10 bit gain setting word for Aux DAC2

00000000

Aux DAC2 Sign

0: Positive

1: Negative

Aux DAC2

Direction

0: Source

1: Sink

Aux DAC2 Sleep

0: Aux DAC1 on

1: Aux DAC 1 off

Auxiliary DAC2

Control and Data

1:0

Aux DAC2 Gain

Adjustment

(9:8) MSB slice of 10 bit gain setting word for Aux DAC2

Cross Point Upper

Delay

7:0

Updelay

Value above zero for upper cross delay (bits 7,6, unused)

00000000

Cross Point Upper

Delay

7:0

Dndelay

Value below zero for lower cross delay (bits 7,6, unused)

00000000

7:3

Cross Control

Clock Delay

Divide rate of CNTCLK by 2^(3:0), CNTCLK = 1/16 DAC clock rate

00000

Wiggle Delay for

Cross Point Control

2:0

Wiggle Delay

Time step in 2^(Wiggle Delay) CNTCLK cycles

000

Cross Run

0: Disables Cross Control loop

1: Enables Cross Control loop

Cross Status (read

only)

0: Control loop is lowering cross point

1: Control loop is raising cross point

Cross Done (read

only)

0: Control loop is chnaging cross point value

1: Control loop is holding cross point value

4:2

Cross Wiggle

(2:0) Number of iterations allowed in control loop

000

Cross Point Control

1:0

Cross Step

(1:0) Value to change cross point value per iteration (wiggle)

Analog Write

7:0

Analog Write

Provides extra writeable control registers for analog circuit

00000000

7:6

Mirror Roll off

Frequency

Mirror Roll off and

band gap Trim

2:0

Band Gap Trim

Temperature

Characteristic

000

Output stack headroom control

Overdrive (current density) trim (temperature packing)

Output Stack

headroom Control

Reference offset from VDD3V (vcas centering)

Analog Status

7:0

Analog Status

Provides extra status register for analog circuitry (unused, read only)

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