LTC2445 datasheet(17/28 Pages) LINER

17 / 28 page

LTC2444/LTC2445/

LTC2448/LTC2449

sn2444589 2444589fs

As described above, CS may be pulled LOW at any time in

order to monitor the conversion status on the SDO pin.

Typically, CS remains LOW during the data output state.

However, the data output state may be aborted by pulling

CS HIGH anytime between the fifth falling edge and the

32nd falling edge of SCK, see Figure 5. On the rising edge

of CS, the device aborts the data output state and imme-

diately initiates a new conversion. Thirteen serial input

data bits are required in order to properly program the

speed/resolution and input channel. If the data output

APPLICATIO S I FOR ATIO

Figure 5. External Serial Clock, Reduced Output Data Length

SCK

(EXTERNAL)

SDI

SDO

BUSY

12345

MSB

BIT 28 BIT 27 BIT 26 BIT 25

SIG

BIT 29

“0”

BIT 30

EOC

Hi-Z

BIT 31

2444 F06

CONVERSION

SLEEP

DATA OUTPUT

CONVERSION

TEST EOC

DON'T CARE

VCC

REF+

REF–

CH0

CH7

CH8

CH15

COM

SCK

SDI

SDO

GND

1,4,5,6,31,32,33

REFERENCE

VOLTAGE

0.1V TO VCC

ANALOG

INPUTS

= EXTERNAL OSCILLATOR

= INTERNAL OSCILLATOR

1µF

2.7V TO 5.5V

LTC2448

4-WIRE

SPI INTERFACE

•

BUSY

DON'T CARE

sequence is aborted prior to the 13th rising edge of SCK,

the new input data is ignored, and the previously selected

speed/resolution and channel are used for the next con-

version cycle. This is useful for systems not requiring all

32 bits of output data, aborting an invalid conversion

cycle or synchronizing the start of a conversion. If a new

channel is being programmed, the rising edge of CS must

come after the 14th falling edge of SCK in order to store

the data input sequence.

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