Data Sheet

LT3073

analog.com

Rev 0.

26 of 37

While the VIOC buffer is inside the switching converter’s feedback loop, given the VIOC buffer’s high bandwidth, the

switching converter’s frequency compensation doesn’t need to be adjusted. Phase delay through the VIOC buffer is

typically less than 2° for frequencies as high as 100kHz; hence, within the switching converter’s bandwidth (usually

much less than 100kHz), the VIOC buffer will be transparent and act like an ideal wire.

For example, for a switching converter with less than 100kHz bandwidth and a phase margin of 50°, using the VIOC

buffer, the phase margin will degrade by at most 2°. Hence, the phase margin for the switching converter (using the

VIOC pin) will be at least 48°. Given that the VIOC buffer is inside the switching converter’s feedback loop, the total

capacitance on the VIOC pin must be below 20pF.

Figure 71.Programming input-to-Output Voltage Differential

As shown in Figure 71, the input-to-output differential voltage is easily programmable to support different

application needs (PSRR vs power dissipation) using the following equation:

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������1+������2

������1

Furthermore, if the LT3073 EN pin shorts to GND, the LT3073 input voltage can rise to the switcher’s input voltage

and thus potentially violate the LT3073’s absolute maximum rating. To prevent this, the maximum LT3073 input

voltage can be set using a resistor (R3) between the VIOC and IN pins of the regulator such that:

������(������������������)������������������������������ = ������������������������������������������������������������������������

������1 + ������2 + ������3

������1

The VIOC pin is capable of sourcing 200µA. Choose R1 and R3 values such that the VIOC pin sources at least 10μA to

ensure system stability.

Figure 76 shows a typical VIOC application used to post-regulate the output of the LT8610A buck converter. The VIOC

voltage is set at 1.1V (VINLDO-VOUTLDO is set to 300mV). The maximum LDO input voltage VINLDO(MAX) is set to 5.08V.

Power Good

The PG pin is an open-drain NMOS output that actively pulls low if EN is low or if any one of these fault modes is

detected:



VOUT is less than 93% of VOUT(NOMINAL) on the rising edge of VOUT.



VOUT is less than 90% of VOUT(NOMINAL) on the falling edge of VOUT.



VBIAS is less than its undervoltage lockout threshold.



The OUT-over-IN voltage detector activates.

51kΩ

806Ω

R1

R2

2.2µF

22µF

4.7µF

800mV

VIN

OUT

BIASF

LT3073

VOUTLDO = 0.5V

IOUT(MAX) = 3A

VO2

VO1

VO0

FB

VBIAS

3.3V

IN

EN

VIOC

MARG

GND

SENSE

TEMP

IMON

POWER

GOOD

BIAS

PG

REF

UPSTREAM

DC TO DC

CONVERTER

V

≥ 1V

VIN

EN/UV

GND

SW

FB

VINLDO

1×

+ –

VFBSWITCHER

R3