QL3012 datasheet(1/14 Pages) ETC1

tên linh kiện	QL3012

Giải thích chi tiết về linh kiện	60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

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60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density

Military Plastic pASIC 3 Family

Rev B

Military pASIC 3 - 3.3V Family

Device Highlights

High Performance and High Density

s

60,000 Usable PLD Gates with 316 I/Os

s

16-bit counter speeds over 300 MHZ, data path

speeds over 400 MHz

s

0.35um four-layer metal non-volatile CMOS

process for smallest die sizes

Easy to Use/Fast Development Cycles

s

100% routable with 100% utilization and complete

pin-out stability

s

Variable-grain logic cells provide high performance

and 100% utilization

s

Comprehensive design tools include high quality

Verilog/VHDL synthesis

Advanced I/O Capabilities

s

Interfaces with both 3.3 volt and 5.0 volt devices

s

PCI compliant with 3.3V and 5.0V buses for -1/-2

speed grades

s

Full JTAG boundary scan

s

Registered I/O cells with individually controlled

clocks and output enables

Features

Total of 180 I/O pins

s

308 bidirectional input/output pins, PCI-compliant

for 5.0 volt and 3.3 volt buses for -1/-2 speed

grades

s

8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

s

Two array clock/control networks available to the

logic cell flip-flop clock, set and reset inputs - each

driven by an input-only pin

s

Up to six global clock/control networks available

to the logic cell F1, clock, set and reset inputs and

the input and I/O register clock, reset and enable

inputs as well as the output enable control - each

driven by an input-only or I/O pin, or any logic cell

output or I/O cell feedback

High Performance

s

Input + logic cell + output total delays under 6 ns

s

Data path speeds exceeding 400 MHz

s

Counter speeds over 300 MHz

TABLE 1: Selector Table

DEVICE HIGHLIGHTS

FEATURES

Device

ASIC

Gates

PLD

Gates

Package

Max

I/O

Qualification

Level

Supply

Voltage

QL3012

8,000

12,000

84PLCC

68

M

3.3V

QL3025

16,000

25,000

208PQFP

174

M

3.3V

QL3040

24,000

40,000

208PQFP

174

M

3.3V

QL3060

36,000

60,000

208PQFP

174

M

3.3V

M = Military Temperature (-55 to +125 degrees C)

Số phần tương tự - QL3012

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
List of Unclassifed Man...	QL3025	528Kb / 17P	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
	QL30250PB256C	528Kb / 17P	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
	QL30250PB256I	528Kb / 17P	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
	QL30250PB256M	528Kb / 17P	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
	QL30250PF144C	528Kb / 17P	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

More results

Mô tả tương tự - QL3012

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
List of Unclassifed Man...	QL8025	739Kb / 49P	LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
	QL4016	478Kb / 18P	16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
	QL2009	272Kb / 12P	3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
	QL4009	373Kb / 18P	9,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
	QL2003	333Kb / 10P	3.3V and 5.0V pASIC-R 2 FPGA Combining Speed, Density, Low Cost and Flexibility
	QL4016-1PB456M	576Kb / 22P	90,000 Usable PLD Gate QuickRAM Combining Performance, Density and Embedded RAM
	QL4058	536Kb / 23P	58,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM
	QL3025	528Kb / 17P	25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
	QL2007	299Kb / 10P	3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility
ATMEL Corporation	ATF16V8B	657Kb / 16P	High Performance Flash PLD

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