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M34D64 bảng dữ liệu(PDF) 9 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  64 Kbit Serial I2C Bus EEPROM With Hardware Write Control on Top Quarter of Memory
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M34D64 bảng dữ liệu(HTML) 9 Page - STMicroelectronics

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M34D64
Sequential Read
This operation can be used after a Current
Address Read or a Random Address Read. The
bus master
does acknowledge the data byte
output, and sends additional clock pulses so that
the device continues to output the next byte in
sequence. To terminate the stream of bytes, the
bus master must
not acknowledge the last byte,
and
must generate a Stop condition, as shown in
Figure 9.
The
output
data
comes
from
consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
counter ‘rolls-over’, and the device continues to
output data from memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9th bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device
terminates the data transfer and switches to its
Stand-by mode.



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