P9412 Datasheet

R35DS0011EU0120 Rev.1.2

Jul.6.21

Page 13

nEN&UVLO

BIAS

MLDO

12-bit ADC

DAC

+Comp

WPC Freq Det

DEMOD

OSC

60MHz

General Purpose IO

(GPIO & GPOD)

BST1

BST2

nEN

LDO5P0

VRECT

AC1

AC2

CM1

CMA

VOUT

ISP

ISN

V1P8_AP

PCLAMP

DEMOD

VRECT

VREF

Is_out

T/RX

control

SCL(OD1);SDA(OD2);/INT(OD3);GPOD4;

GPOD5;GPIO0;GPIO1;GPIO2;GPIO3;GPIO4;GPIO5

-

ARM M0 Controller

LDO5V

CPBST2

(w / 24kBMTP, 8 kB RAM)

CM2

CMB

Capacitive

Divider

Control

CPBST3

CPP

CPBST1

CPOUT

CPN

+

-

Is_ext

Is_out

PDET

VOUT_S

VREF

+

_

CPGND

PGND

LDO1P8

LDO1P8

V5P0_AP

5V Select

GND

PCLAMP_DR

LDO5P0

TxEN

VSENSE

OD6

Q6 (A)

Q1

Q3

Q4

Q2

Q5

Q9 (D)

Q8 (C)

Q7 (B)

/EN

OD0

OVP

Figure 4. Simplified Block Diagram

3.2.2.

Power Control

The voltage at VRECT and the current through the rectifier are sampled periodically and digitized by the ADC.

The digital equivalents of the voltage and current are supplied to the internal control logic, which decides

whether the loading conditions on VRECT indicate that a change in the operating point is required. If the load is

heavy enough to bring the voltage at VRECT below its target, the transmitter is instructed to move its frequency

lower, closer to resonance. If the voltage at VRECT is higher than its target, the transmitter is instructed to

increase its frequency. To maximize efficiency, the voltage at VRECT is programmed to decrease as the LDO’s

load current increases.

3.3

Status and Interrupt Indicators

The P9412 has seven General Purpose Open Drain (GPOD) pins and six General Purpose Input Output (GPIO)

pins. The GP pins can be configured to meet a wide variety of signaling and sensing requirements in end

applications. The GPIO pins can be push-pull input/outputs and the GPOD pins can be open-drain

inputs/outputs. These digital pins are internally biased or referenced to one of the 1.8V voltage rails. The GPIO

pins must not be directly connected to GND to avoid overcurrent conditions forced upon the output. Resistive

pull-

downs on the GPIO pins should be ≥ 2kΩ. When any of the GPOD or GPIO pins are used for analog voltage

measurements using the internal ADC, the voltage should be limited to < 1.8V in order to avoid saturating the

ADC or forcing a voltage above the reference voltage rail. The most common uses have been designated in the

reference schematic and the reference schematic should be followed to align with the latest firmware unless

written exception is provided.