Philips Semiconductors

Product specification

74F595

8-bit shift register with output latches (3-State)

2

1990 Apr 18

853–1096 99392

FEATURES

(20

µA in High and Low states)

DESCRIPTION

The 74F595 contains an 8-bit serial-in, parallel-out shift register that

feeds an 8-bit D-type storage register. The storage register has

parallel 3-State outputs. Separate clocks are provided for both the

shift register and the storage register. The shift register has a direct

overriding clear, serial input and serial output pins for cascading.

Both the shift register and storage register clocks are positive

edge-triggered. If the user wishes to connect both clocks together,

the shift register state will always be one clock pulse ahead of the

storage register.

This device uses patented circuitry to control system noise and

internal ground bounce. This is done by eliminating switching

feedthrough current and controlling both Low-to-High and

High-to-Low slew rates.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

Q7

STCP

SHCP

SHR

OE

Q0

DS

Q1

Q2

Q6

Q3

Q4

Q5

SF01096

9

8

GND

QS

TYPE

TYPICAL SUPPLY CURRENT

(TOTAL)

74F595

130MHz

65mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F595N

SOT38-4

16-pin plastic SO

N74F595D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

Ds

Serial data input

1.0/0.033

20

µA/20µA

SHCP

Shift register clock pulse input (active rising edge)

1.0/0.033

20

µA/20µA

STCP

Storage register clock pulse input (active rising edge)

1.0/0.033

20

µA/20µA

SHR

Shift register reset input (active Low)

1.0/0.033

20

µA/20µA

OE

Output Enable input (active Low)

1.0/0.033

20

µA/20µA

Qs

Serial expansion output

50/33

1.0mA/20mA

Q0–Q7

Data outputs

150/40

3.0mA/24mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.