Philips Semiconductors

Product specification

74F51

Dual 2-wide 2-input, 2-wide 3-input AND-OR-invert gate

2

March 3, 1989

853–0054 95962

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F51

3.0ns

3.5mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

14-pin plastic DIP

N74F51N

SOT27-1

14-pin plastic SO

N74F51D

SOT108-1

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

D0e

D0d

Q0

D0f

D0c

D0b

D0a

D1a

Q1

D1b

D1c

D1d

SF00085

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

Dna, Dnb, Dnc, Dnd, Dne, Dnf

Data inputs

1.0/1.0

20

µA/0.6mA

Q0, Q1

Data outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

D1a

D0f

D0b D0c D0d

D1b D1c

D0e

Q0

Q1

86

12

13

9

10

11

2

3

4

GND = Pin 7

SF00086

D0a

1

D1d

5

IEC/IEEE SYMBOL

SF00087

1

8

6

9

10

11

13

12

1

2

3

4

5

1

&

&

&

&

LOGIC DIAGRAM

GND = Pin 7

SF00088

1

12

13

2

3

D0a

D0b

D0c

D1a

D1b

Q0

8

9

10

11

D0d

D0e

D0f

4

5

D1c

D1d

Q1

6

FUNCTION TABLE FOR 3-INPUT GATES

INPUTS

OUTPUT

D0a

D0b

D0c

D0d

D0e

D0f

Q0

H

H

H

X

X

X

L

X

X

X

H

H

H

L

All other combinations

H

NOTES:

H = High voltage level

L

= Low voltage level

X = Don’t care

FUNCTION TABLE FOR 2-INPUT GATES

INPUTS

OUTPUT

D1a

D1b

D1c

D1d

Q1

H

H

X

X

L

X

X

H

H

L

All other combinations

H

NOTES:

H = High voltage level

L

= Low voltage level

X = Don’t care