74F50109 datasheet(8/12 Pages) PHILIPS

8 / 12 page

Philips Semiconductors

Product specification

74F50109

Synchronizing dual J–K positive edge-triggered

flip-flop with metastable immune characteristics

September 14, 1990

AC WAVEFORMS

CPn

tsu(H)

th(H)

Jn, Kn

tw(H)

1/fmax

tsu(L)

th(L)

tPLH

tw(L)

tPHL

tPLH

SF00139

Waveform 1. Propagation delay for data to output, data

setup time and hold times, and clock

width, and maximum clock frequency

SDn or RDn

trec

CPn

SF00603

Waveform 3. Recovery time for set or reset to output

RDn

tPLH

tw(L)

tPHL

tPLH

SDn

tw(L)

SF00050

Waveform 2. Propagation delay for set and reset to output,

set and reset pulse width

Qn, Qn

tsk(o)

Qn, Qn

SF00590

Waveform 4. Output skew

NOTES:

For all waveforms, VM = 1.5V.

The shaded areas indicate when the input is permitted to change for

predictable output performance.

TEST CIRCUIT AND WAVEFORM

90%

10%

90%

10%

90%

10%

90%

10%

NEGATIVE

PULSE

POSITIVE

PULSE

AMP (V)

tTHL (tf )

INPUT PULSE REQUIREMENTS

rep. rate

tTLH

tTHL

1MHz

500ns

2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.

PULSE

GENERATOR

VIN

VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:

RL = Load resistor;

see AC ELECTRICAL CHARACTERISTICS for value.

CL = Load capacitance includes jig and probe capacitance;

see AC ELECTRICAL CHARACTERISTICS for value.

RT = Termination resistance should be equal to ZOUT of

pulse generators.

tTHL (tf )

tTLH (tr )

AMP (V)

amplitude

3.0V

1.5V

SF00006

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