MCP3465RT-ESLASHSFX datasheet(31/110 Pages) MICROCHIP

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DS20006414C-page 31

MCP3465R

4.0

TERMINOLOGY AND

FORMULAS

This section defines the terms and formulas used

throughout this document. The following terms are

defined:

• MCLK – Master Clock

• AMCLK – Analog Master Clock

• DMCLK – Digital Master Clock

• DRCLK – Data Rate Clock

• OSR – Oversampling Ratio

• Offset Error

• Gain Error

• Integral Nonlinearity Error (INL)

• Signal-to-Noise Ratio (SNR)

• Signal-to-Noise and Distortion Ratio (SINAD)

• Total Harmonic Distortion (THD)

• Spurious-Free Dynamic Range (SFDR)

• MCP3465R Delta-Sigma Architecture

• Power Supply Rejection Ratio (PSRR)

• Common-Mode Rejection Ratio (CMRR)

• Digital Pins Output Current Consumption

FIGURE 4-1:

System Clock Details.

4.1

MCLK – Master Clock

This is the master clock frequency used for clocking the

Delta-Sigma ADC and the timer for the Scan mode. It

can be externally generated (in which case, SCK is the

input pin for this clock) or internally generated by the

internal oscillator (in which case, it can also be clocked

out on the SCK pin).

4.2

AMCLK – Analog Master Clock

This is the clock frequency that is present on the analog

portion of the device after prescaling has occurred via

the PRE[1:0] bits.

EQUATION 4-1:

ANALOG MASTER

CLOCK

4.3

DMCLK – Digital Master Clock

This is the clock frequency that is present on the digital

portion of the device. This is also the sampling frequency

or the rate at which the modulator outputs are refreshed.

Each period of this clock corresponds to one sample and

one modulator output. See Equation 4-2.

EQUATION 4-2:

DIGITAL MASTER CLOCK

4.4

DRCLK – Data Rate Clock

This is the output data rate in Continuous mode or the

rate at which the ADC outputs new data. This data rate

depends on the OSR and the prescaler as shown in

Equation 4-3.

EQUATION 4-3:

DATA RATE

Since this is the output data rate and since the

decimation filter is a sinc (or notch) filter, there is a

notch in the filter transfer function at each integer

multiple of this rate.

SCK

Pad

1/OSR

Internal Oscillator

MCLK

Multiplexer

OUT

1/PRESCALE

1/4

AMCLK

DMCLK

DRCLK

Clock Divider

OSR[3:0]

PRE[1:0]

CLK_SEL[1]

AMCLKOUT

CLK_SEL[1] =

CLK_SEL[1:0] =

AMCLK

MCLK

Prescale

-----------------------

DMCLK

AMCLK

---------------------

MCLK

4 Prescale



--------------------------------

DRCLK

DMCLK

OSR

----------------------

AMCLK

4OSR



---------------------

MCLK

4 OSR Prescale



---------------------------------------------------

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