74ALVC16245DGG datasheet(2/10 Pages) PHILIPS

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Philips Semiconductors

Product specification

74ALVC16245/

74ALVCH16245

16-bit bus transceiver with direction pin (3-State)

1998 Jun 29

853-2083 19638

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple V

CC and ground pins for minimum noise

and ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold (74ALVCH16245 only)

• Output drive capability 50Ω transmission lines @ 85°C

• Current drive ±24 mA at 3.0 V

DESCRIPTION

The 74ALVC16245(74ALVCH16245) is a 16-bit transceiver featuring

non-inverting 3-State bus compatible outputs in both send and

receive directions.

The 74ALVC16245(74ALVCH16245) features two output enable

(nOE) inputs for easy cascading and two send/receive (nDIR) inputs

for direction control. nOE controls the outputs so that the buses are

effectively isolated. This device can be used as two 8-bit

transceivers or one 16-bit transceiver.

The 74ALVCH16245 has active bus hold circuitry which is provided

to hold unused or floating data inputs at a valid logic level. This

feature eliminates the need for external pull-up or pull-down

resistors.

The 74ALVC16245 has 5V tolerant inputs.

PIN CONFIGURATION

GND

VCC1

GND

VCC1

2A5

2A4

VCC2

2A3

2A2

GND

2A1

2A0

1A7

1A6

GND

1A5

1A4

VCC2

1A3

1A2

GND

1A1

1A0

1OE

GND

2DIR

2OE

2A7

2A6

GND

SW00198

1DIR

1B0

1B1

1B2

1B3

1B4

1B5

1B6

1B7

2B0

2B1

2B2

2B3

2B4

2B5

2B6

2B7

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

Propagation delay

An to Bn;

Bn to An

VCC = 2.5V, CL = 30pF

VCC = 3.3V, CL = 50pF

1.9

Input capacitance

4.0

CI/O

Input/output capacitance

8.0

Power dissipation capacitance per buffer

V = GND to VCC1

Outputs enabled

CPD

Power dissipation capacitance per buffer

VI = GND to VCC1

Outputs disabled

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of the outputs.

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH AMERICA

NORTH AMERICA

DWG NUMBER

48-Pin Plastic SSOP Type III

–40

°C to +85°C

74ALVC16245 DL

AC16245 DL

SOT370-1

48-Pin Plastic TSSOP Type II

–40

°C to +85°C

74ALVC16245 DGG

AC16245 DGG

SOT362-1

48-Pin Plastic SSOP Type III

–40

°C to +85°C

74ALVCH16245 DL

ACH16245 DL

SOT370-1

48-Pin Plastic TSSOP Type II

–40

°C to +85°C

74ALVCH16245 DGG

ACH16245 DGG

SOT362-1

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