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MPC855T bảng dữ liệu(PDF) 64 Page - NXP Semiconductors

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MPC860 PowerQUICC Family Hardware Specifications, Rev. 10
64
Freescale Semiconductor
CPM Electrical Characteristics
11.12 I2C AC Electrical Specifications
Table 26 provides the I2C (SCL < 100 kHz) timings.
Table 27 provides the I2C (SCL > 100 kHz) timings.
Table 26. I2C Timing (SCL < 100 kHZ)
Num
Characteristic
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
0
100
kHz
200
SCL clock frequency (master)1
1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3
× pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK/pre_scaler) must be greater than or equal to 4/1.
1.5
100
kHz
202
Bus free time between transmissions
4.7
—
μs
203
Low period of SCL
4.7
—
μs
204
High period of SCL
4.0
—
μs
205
Start condition setup time
4.7
—
μs
206
Start condition hold time
4.0
—
μs
207
Data hold time
0
—
μs
208
Data setup time
250
—
ns
209
SDL/SCL rise time
—
1
μs
210
SDL/SCL fall time
—
300
ns
211
Stop condition setup time
4.7
—
μs
Table 27. . I2C Timing (SCL > 100 kHZ)
Num
Characteristic
Expression
All Frequencies
Unit
Min
Max
200
SCL clock frequency (slave)
fSCL
0
BRGCLK/48
Hz
200
SCL clock frequency (master)1
1 SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3)
× pre_scaler × 2).
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1.
fSCL
BRGCLK/16512
BRGCLK/48
Hz
202
Bus free time between transmissions
1/(2.2 * fSCL)
—
s
203
Low period of SCL
1/(2.2 * fSCL)
—
s
204
High period of SCL
1/(2.2 * fSCL)
—
s
205
Start condition setup time
1/(2.2 * fSCL)
—
s
206
Start condition hold time
1/(2.2 * fSCL)
—
s
207
Data hold time
0
—
s
208
Data setup time
1/(40 * fSCL)
—
s
209
SDL/SCL rise time
—
1/(10 * fSCL)
s
210
SDL/SCL fall time
—
1/(33 * fSCL)
s
211
Stop condition setup time
1/2(2.2 * fSCL)
—
s



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