ADSP-TS101S datasheet(7/44 Pages) AD

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REV. A

ADSP-TS101S

to occur while the DSP’s core continues to execute program

instructions. The DMA controller performs DMA transfers

between:

• Internal memory and external memory and memory-

mapped peripherals

• Internal memory of other DSPs on a common bus, a host

processor, or link port I/O

• External memory and external peripherals or link port I/O

• External bus master and internal memory or link port I/O

The DMA controller provides a number of additional features.

The DMA controller supports Flyby transfers. Flyby operations

only occur through the external port (DMA channel 0) and do

not involve the DSP’s core. The DMA controller acts as a conduit

to transfer data from one external device to another through

external memory. During a transaction, the DSP:

• Relinquishes the external data bus

• Outputs addresses, memory selects (MS1–0, MSSD,

RAS, CAS, and SDWE) and the FLYBY, IOEN, and

RD/WR strobes

• Responds to ACK

DMA chaining is also supported by the DMA controller. DMA

chaining operations enable applications to automatically link one

DMA transfer sequence to another for continuous transmission.

The sequences can occur over different DMA channels and have

different transmission attributes.

Figure 3. Shared Memory Multiprocessing System

CLKS/REFS

ADDR31–0

DATA63–0

BR1

BR7–2,0

ADDR31–0

DATA63–0

BR0

BR7–1

BMS

CONTROL

ADSP-TS101 #0

CONTROL

ADSP-TS101 #1

ADSP-TS101 #7

ADSP-TS101 #6

ADSP-TS101 #5

ADSP-TS101 #4

ADSP-TS101 #3

ADSP-TS101 #2

RESET

ID2–0

CLKS/REFS

LCLK_P

S/LCLK_N

VREF

SCLK_P

LCLKRAT2–0

SCLKFREQ

000

CLOCK

REFERENCE

VOLTAGE

ADDR

DATA

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

ACK

GLOBAL

MEMORY

AND

PERIPHERALS

(OPTIONAL)

ADDR

DATA

ADDR

DATA

BOOT

EPROM

(OPTIONAL)

MS1–0

ACK

ID2–0

001

HBG

HBR

WRH/L

SDRAM

MEMORY

(OPTIONAL)

MSSD

FLYBY

IOEN

RAS

CAS

LDQM

HDQM

SDWE

SDCKE

SDA10

RAS

CAS

DQM

CKE

A10

ADDR

DATA

CLK

MSH

DMAR3–0

DPA

BOFF

CPA

BRST

LINK

DEVICES

(4 MAX)

(OPTIONAL)

LXCLKIN

LXDIR

LXDAT7–0

LXCLKOUT

TMR0E

CONTROLIMP2–0

LINK

IRQ3–0

FLAG3–0

LINK

RESET

BUSLOCK

CLOCK

DS2–0

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