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MCP6V86 bảng dữ liệu(PDF) 21 Page - Microchip Technology

tên linh kiện MCP6V86
Giải thích chi tiết về linh kiện  5 MHz, 0.5 mA, Zero-Drift Op Amps
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DS20006398A-page 21
MCP6V86/6U/7/9
4.2.1.3
Input Current Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute Maxi-
mum Ratings†”). This requirement is independent of
the voltage limits discussed previously.
Figure 4-6 shows one approach to protecting these
inputs. The R1 and R2 resistors limit the possible cur-
rent in or out of the input pins (and into D1 and D2). The
diode currents will dump onto VDD.
FIGURE 4-6:
Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of the
R1 and R2 resistors. In this case, the currents through
the D1 and D2 diodes need to be limited by some other
mechanism. The resistors then serve as inrush current
limiters; the DC current into the input pins (VIN+ and
VIN-) should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common-
mode Input Voltage (VCM) is below ground (VSS); see
Figure 2-15.
4.2.2
RAIL-TO-RAIL OUTPUT
The output voltage range of the MCP6V86/6U/7/9
devices’ zero-drift op amps is VDD – 5 mV (typical), and
VSS + 5 mV (typical) when RL = 10 kΩ is connected to
VDD/2 and VDD = 5.5V. Refer to Figures 2-17 and 2-18
for more information.
This op amp is designed to drive light loads; use
another amplifier to buffer the output from heavy loads.
4.3
Application Tips
4.3.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1-1 gives both the linear and quadratic
Temperature Coefficients (TC1 and TC2) of the input
offset voltage. The input offset voltage, at any tempera-
ture in the specified range, can be calculated as fol-
lows:
EQUATION 4-1:
4.3.2
OFFSET AT POWER-UP
When these parts power up, the Input Offset (VOS)
starts at its uncorrected value. Circuits with high DC
gain can cause the output to reach one of the two rails.
In this case, the time to a valid output is delayed by an
Output Overdrive Time (like tODR) in addition to the
Start-up Time (like tSTR).
It can be simple to avoid this extra start-up time. Reduc-
ing the gain is one method; adding a capacitor across
the Feedback Resistor (RF) is another method.
V1
R1
VDD
D1
min(R1,R2)>
VSS –min(V1,V2)
2mA
VOUT
V2
R2
D2
min(R1,R2)>
max(V1,V2)– VDD
2mA
U1
MCP6V8X
+
–
VOS TA

VOS TC1TTC2T
2
++
=
Where:
T =TA –+25°C
VOS(TA) = Input offset voltage at TA
VOS = Input offset voltage at +25°C
TC1 = Linear temperature coefficient
TC2 = Quadratic temperature coefficient



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