DRA821U2...ALM datasheet(218/252 Pages) TI

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Table 7-82. Debug Trace Switching Characteristics (continued)

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

DBTR3

tw(TRC_CLKL)

Pulse width, TRC_CLK low

2.50

DBTR4

tosu(TRC_DATAV-

TRC_CLK)

Output setup time, TRC_DATA valid to TRC_CLK edge

0.81

DBTR5

toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid

0.81

DBTR6

tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge

0.81

DBTR7

toh(TRC_CLK-TRC_CTLI)

Output hold time, TRC_CLK edge to TRC_CTL invalid

0.81

3.3 V Mode

DBTR1

tc(TRC_CLK)

Cycle time, TRC_CLK

9.75

DBTR2

tw(TRC_CLKH)

Pulse width, TRC_CLK high

4.13

DBTR3

tw(TRC_CLKL)

Pulse width, TRC_CLK low

4.13

DBTR4

tosu(TRC_DATAV-

TRC_CLK)

Output setup time, TRC_DATA valid to TRC_CLK edge

1.22

DBTR5

toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid

1.22

DBTR6

tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge

1.22

DBTR7

toh(TRC_CLK-TRC_CTLI)

Output hold time, TRC_CLK edge to TRC_CTL invalid

1.22

TRC_DATA

TRC_CTL

TRC_CLK

(

)

(

)

(Ideal)

Worst Case 1

Worst Case 2

DBTR1

DBTR2

DBTR3

DBTR4

DBTR6

DBTR5

DBTR7

DBTR4

DBTR6

DBTR5

DBTR7

SPRSP08_Debug_01

Figure 7-112. Debug Trace Timing

7.9.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)

For more details about features and additional description information on the device IEEE 1149.1 Standard–

Test–Access Port, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8,

Detailed Description.

Table 7-83 represents JTAG timing conditions.

Note

The JTAG signals are split across two IO power domains on the device. Timings parameters defined

in this section only apply when the two IO power domains are operating at the same voltage and level-

shifters are not inserted into the signal path. Values for the following timing parameters are not defined

when operating the two IO power domains at different voltages since propagation delay through the

device IO buffers differ when some are operating at 1.8V while others are operating at 3.3V. This

effectively reduces timing margin beyond the values defined in this section. The JTAG interface is still

expected to function when the two IO power domains are operated at different voltages, assuming the

system designer has implemented appropriate level-shifters and the operating frequency is reduced

to accommodate additional delay inserted by the level-shifters and IO buffers operating at different

voltages

DRA821U-Q1

SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022

www.ti.com

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