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DRA821U4...ALM bảng dữ liệu(PDF) 108 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  DRA821 Jacinto™ Processors
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7.9 Timing and Switching Characteristics
Note
The timings presented in this section are valid when the DRV_STR (Drive Strength) control in the
associated PADCONFIG registers are set to the default “0h – Nominal (recommended)” value.
7.9.1 Timing Parameters and Information
The timing parameter symbols used in Section 7.9 are created in accordance with JEDEC Standard 100. To
shorten the symbols, some pin names and other related terminologies have been abbreviated in Table 7-3:
Table 7-3. Timing Parameters Subscripts
SYMBOL
PARAMETER
c
Cycle time (period)
d
Delay time
dis
Disable time
en
Enable time
h
Hold time
su
Setup time
START
Start bit
t
Transition time
v
Valid time
w
Pulse duration (width)
X
Unknown, changing, or don't care level
F
Fall time
H
High
L
Low
R
Rise time
V
Valid
IV
Invalid
AE
Active Edge
FE
First Edge
LE
Last Edge
Z
High impedance
DRA821U-Q1
SPRSP57D – APRIL 2020 – REVISED DECEMBER 2022
www.ti.com
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