MOTOROLA

MPC823e Mobile Computing Microprocessor

7

Architecture

The MPC823e microprocessor uses a dual-processor architecture design approach with large data

and instruction caches to provide high-performance using a general-purpose RISC integer

processor and a special-purpose 32-bit scalar RISC communication processor module. The

peripherals are uniquely designed for communication requirements and can provide embedded

signal processing functions for communication and user interface enhancements and the I/O

support needed for high-speed digital communication.

The MPC823e is comprised of four main modules that interface with the 32-bit internal bus:

•

The embedded PowerPC core

•

The system interface unit

•

The communication processor module

•

LCD controller

32-BITRISCMICROCONTROLLER

ANDPROGRAMROM

INSTRUCTION

BUS

MMU

INSTRUCTION

16K

INSTRUCTION

MMU

DATA

8K

DATACACHE

LOAD/STORE

BUS

GENERAL

INTERRUPT

CONTROLLER

FOUR

TIMERS

TIMER

DUAL-PORT

RAM

MAC

GENERATORS

BAUDRATE

VIRTUALSERIAL

AND

INDEPENDENT

DMACHANNELS

LCDANDVIDEO

CONTROLLERS

PCMCIAINTERFACE

REAL-TIMECLOCK

SYSTEMFUNCTIONS

MEMORYCONTROLLER

INTERNAL

BIU

EXTERNAL

BIU

SYSTEMINTERFACEUNIT

USB

SCC2

SPI

I

2

C

SMC1

SMC2

SERIALINTERFACE

TIMESLOTASSIGNERS

8K

CACHE

POWERPC

CORE

PURPOSE I/O

SCC3

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com