LIS2L02AS4

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Table 2. Pin Description

Figure 3. Pin Connection (Top view)

N°

Pin

Function

1 to 5

NC

Internally not connected

6GND

0V supply

7

Vdd

Power supply

8

Vouty

Output Voltage

9

ST

Self Test (Logic 0: normal mode; Logic 1: Self-test)

10

Voutx

Output Voltage

11

PD

Power Down (Logic 0: normal mode; Logic 1: Power-Down mode)

12

NC

Internally not connected

13

FS

Full Scale selection (Logic 0: 2g Full-scale; Logic 1: 6g Full-scale)

14-15

Reserved

Leave unconnected or connect to Vdd

16

Reserved

Connect to Vdd or ground

17

Reserved

Leave unconnected or connect to Vdd

18

Reserved

Leave unconnected or connect to ground

19 to 24

NC

Internally not connected

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

1

13

NC

NC

NC

NC

NC

Vdd

GND

Vouty

ST

RESERVED

RESERVED

RESERVED

NC

NC

NC

NC

NC

NC

1

3

2

4

5

6

7

8

9

22

21

20

19

18

16

17

15

23

10

24

Voutx

RESERVED

D05IN1544

PD

RESERVED

11

14

13

12

NC

FS

Y

X