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ICS952011 bảng dữ liệu(PDF) 13 Page - Integrated Circuit Systems

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13
Integrated
Circuit
Systems, Inc.
ICS952011
0721A—07/29/03
I
2C Table: Reserved Register
Control
Function
Bit 7
Reserved
Reserved
RW
-
-
1
Bit 6
Reserved
Reserved
RW
-
-
1
Bit 5
Reserved
Reserved
RW
-
-
1
Bit 4
Reserved
Reserved
RW
-
-
1
Bit 3
Reserved
Reserved
RW
-
-
1
Bit 2
Reserved
Reserved
RW
-
-
1
Bit 1
Reserved
Reserved
RW
-
-
1
Bit 0
Reserved
Reserved
RW
-
-
1
I
2C Table: Frequency Select Register
Control
Function
Bit 7
FS3
Freq Select Bit 7
RW
0
Bit 6
FS2
Freq Select Bit 6
RW
0
Bit 5
FS1
Freq Select Bit 5
RW
0
Bit 4
FS0
Freq Select Bit 4
RW
0
Bit 3
FS Source
Frequency HW/IIC Select
RW
Latch Input
IIC
0
Bit 2
FS4
Freq Select Bit 2
RW
0
Bit 1
SS_EN
Spread Enable
RW
OFF
ON
1
Bit 0
Outputs
Output Control
RW
Running
Tri-state
0
I
2C Table: Read Back Register
Control
Function
Bit 7
WDHRB
WD Hard Alarm Status
Read back
RNormal
Alarm
X
Bit 6
WDSRB
WD Soft Alarm Status
Read back
RNormal
Alarm
X
Bit 5
MULTISEL
Multisel Read back
R
-
-
X
Bit 4
FS4RB
FS4 Read back
R
-
-
X
Bit 3
FS3RB
FS3 Read back
R
-
-
X
Bit 2
FS2RB
FS2 Read back
R
-
-
X
Bit 1
FS1RB
FS1 Read back
R
-
-
X
Bit 0
FS0RB
FS0 Read back
R
-
-
X
I
2C Table: Output Control Register
Control
Function
Bit 7
ZCLK_1
Output Control
RW
Disable
Enable
1
Bit 6
ZCLK_0
Output Control
RW
Disable
Enable
1
Bit 5
PCI_F0
PCI_STOP# Control
RW
Stop Disable
Stop Enable
0
Bit 4
PCI_F1
PCI_STOP# Control
RW
Stop Disable
Stop Enable
0
Bit 3
CPUT0/C0
CPU_STOP# Control
RW
Stop Disable
Stop Enable
1
Bit 2
CPUT1/C1
CPU_STOP# Control
RW
Stop Disable
Stop Enable
1
Bit 1
CPUT0/C0
Output Control
RW
Disable
Enable
1
Bit 0
CPUT1/C1
Output Control
RW
Disable
Enable
1
01
01
0
0
PWD
PWD
1
1
Type
PWD
PWD
Name
Type
See Table1 : Quad Rom
Frequency Selection Table
See Table1
Type
Byte 3
Pin #
-
-
-
-
-
-
-
-
Name
Type
Byte 4
Pin #
-
-
-
-
-
-
-
Byte 5
Pin #
Name
-
-
-
-
-
-
-
-
Name
9
40, 39
44, 43
14
15
10
Byte 6
Pin #
40, 39
44, 43



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