ADC12DL080 datasheet(21/24 Pages) NSC

21 / 24 page

Applications Information (Continued)

4.0 POWER SUPPLY CONSIDERATIONS

The power supply pins should be bypassed with a 10 µF

capacitor and with a 0.1 µF ceramic chip capacitor near each

power pin. Leadless chip capacitors are preferred because

they have low series inductance.

As is the case with all high-speed converters, the

ADC12DL080 is sensitive to power supply noise. Accord-

ingly, the noise on the analog supply pin should be kept

below 100 mV

P-P.

No pin should ever have a voltage on it that is in excess of

the supply voltages, not even on a transient basis. Be espe-

cially careful of this during power turn on and turn off.

The V

DR pin provides power for the output drivers and may

be operated from a supply in the range of 2.4V to V

D. This

can simplify interfacing to lower voltage devices and sys-

tems. Note, however, that t

OD increases with reduced VDR.

DO NOT operate the V

DR pin at a voltage higher than VD.

5.0 LAYOUT AND GROUNDING

Proper grounding and proper routing of all signals are es-

sential to ensure accurate conversion. Maintaining separate

analog and digital areas of the board, with the ADC12DL080

between these areas, is required to achieve specified per-

formance.

The ground return for the data outputs (DR GND) carries the

ground current for the output drivers. The output current can

20169413

FIGURE 4. Application Circuit using Transformer Drive Circuit

20169418

FIGURE 5. Optional Amplifier Drive for Circuit in Figure 4

ADC12DL080 bảng dữ liệu(PDF) 21 Page - National Semiconductor (TI)