XRT75R06DIB datasheet(4/105 Pages) EXAR

4 / 105 page

XRT75R06D

áç

SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER

REV. 1.0.0

TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................. 1

APPLICATIONS .............................................................................................................................................. 1

Figure 1. Block Diagram of the XRT 75R06D ................................................................................................... 1

ORDERING INFORMATION ................................................................................................................... 1

FEATURES .................................................................................................................................................... 2

TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2

RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2

Figure 2. XRT75R06D in BGA package (Bottom View) .................................................................................... 3

TABLE OF CONTENTS .................................................................................................................................... I

PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4

TRANSMIT INTERFACE ................................................................................................................................... 4

RECEIVE INTERFACE ..................................................................................................................................... 6

CLOCK INTERFACE ........................................................................................................................................ 8

CONTROL AND ALARM INTERFACE ....................................................................................................... 9

ANALOG POWER AND GROUND ................................................................................................................... 12

DIGITAL

POWER AND GROUND ..................................................................................................................... 14

FUNCTIONAL DESCRIPTION ......................................................................................... 16

1.0 R3 Technology (reconfigurable, relayless redundancy) ............................................................... 16

1.1 NETWORK ARCHITECTURE ................................................................................................................................ 16

Figure 3. Network Redundancy Architecture ................................................................................................. 16

2.0 clock Synthesizer ............................................................................................................................. 17

2.1 CLOCK DISTRIBUTION ....................................................................................................................................... 17

Figure 5. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... 17

Figure 4. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 17

3.0 The Receiver Section ....................................................................................................................... 18

Figure 6. Receive Path Block Diagram ........................................................................................................... 18

3.1 RECEIVE LINE INTERFACE ................................................................................................................................. 18

Figure 7. Receive Line InterfaceConnection ................................................................................................... 18

3.2 ADAPTIVE GAIN CONTROL (AGC) ..................................................................................................................... 19

3.3 RECEIVE EQUALIZER ........................................................................................................................................ 19

Figure 8. ACG/Equalizer Block Diagram ......................................................................................................... 19

3.3.1 Recommendations for Equalizer Settings ....................................................................................... 19

3.4 CLOCK AND DATA RECOVERY .......................................................................................................................... 19

3.4.1 Data/Clock Recovery Mode ............................................................................................................... 19

3.4.2 Training Mode ..................................................................................................................................... 19

3.5 LOS (LOSS OF SIGNAL) DETECTOR .................................................................................................................. 20

3.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 20

3.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 20

TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF

LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 20

3.5.3 E3 LOS Condition: ............................................................................................................................. 21

Figure 9. Loss Of Signal Definition for E3 as per ITU-T G.775 ....................................................................... 21

Figure 10. Loss of Signal Definition for E3 as per ITU-T G.775. ..................................................................... 21

3.5.4 Interference Tolerance ....................................................................................................................... 22

Figure 11. Interference Margin Test Set up for DS3/STS-1 ............................................................................ 22

Figure 12. Interference Margin Test Set up for E3. ......................................................................................... 22

TABLE 2: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 23

3.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 24

3.6 B3ZS/HDB3 DECODER .................................................................................................................................... 24

Figure 13. Receiver Data output and code violation timing ............................................................................ 24

4.0 The Transmitter Section .................................................................................................................. 25

Figure 14. Transmit Path Block Diagram ........................................................................................................ 25

4.1 TRANSMIT DIGITAL INPUT INTERFACE ................................................................................................................ 25

XRT75R06DIB bảng dữ liệu(PDF) 4 Page - Exar Corporation

XRT75R06DIB bảng dữ liệu(HTML) 4 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL