XRT71D03 datasheet(21/24 Pages) EXAR

21 / 24 page

áç

XRT71D03

3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR

REV. 1.2.0

the falling edge of SClk Cycle #8 (see Figure 11) the

serial data output signal (SDO) becomes active. At

this point the user can begin reading the data con-

tents of the addressed Command Register (at Ad-

dress [A4, A3, A2, A1, A0]) via the SDO output pin.

The Serial Interface will output this eight bit data word

(D0 through D7) in ascending order (with the LSB

first), on the falling edges of the SClk. The data (on

the SDO output pin) is stable for reading on the very

next rising edge of the SClk.

3.1.6

Write Operation

Once the last address bit (A4) has been clocked into

the SDI input, the Write operation will proceed

through an idle period, lasting three SClk periods. Pri-

or to the rising edge of SClk Cycle #9, the eight bit

data word is applied to SDI input. Data on SDI is

latched on the rising edge of SClk.

NOTES:

1. A5 is always “0”.

2. R/W = “1” for Read Operations

3. R/W = “0” for Write Operations

4. Denotes a “don’t care” value (shaded areas)

3.1.7

Simplified Interface Option

The user can simplify the design of the circuitry con-

necting to the Microprocessor Serial Interface by ty-

ing both the SDO and SDI pins together, and reading

data from and/or writing data to this combined signal.

This simplification is possible because only one of

FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE

High Z

SDO

R/W

SDI

1234567

1 0

1 1

1 2

1 3

1 4

1 5

1 6

SClk

High Z

XRT71D03 bảng dữ liệu(PDF) 21 Page - Exar Corporation

XRT71D03 bảng dữ liệu(HTML) 21 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

bảng dữ liệu tải về

Link URL