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SST26WF040BAT-104I/CS bảng dữ liệu(PDF) 45 Page - Microchip Technology |
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SST26WF040BAT-104I/CS bảng dữ liệu(HTML) 45 Page - Microchip Technology |
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45 / 96 page  2014-2017 Microchip Technology Inc. DS20005283C-page 45 SST26WF040B/040BA SST26WF080B/080BA 8.0 AC CHARACTERISTICS FIGURE 8-1: HOLD TIMING DIAGRAM TABLE 8-1: AC OPERATING CHARACTERISTICS (VDD = 1.65V–1.95V) Symbol Parameter Limits - 40 MHz Limits - 80 MHz Limits - 104 MHz Units MinMax MinMax MinMax FCLK Serial Clock Frequency 40 80 104 MHz TCLK Serial Clock Period 25 12.5 9.6 ns TSCKH Serial Clock High Time 11 5.5 4.5 ns TSCKL Serial Clock Low Time 11 5.5 4.5 ns TSCKR1 1. Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements Serial Clock Rise Time (slew rate) 0.1 0.1 0.1 V/ns TSCKF1 Serial Clock Fall Time (slew rate) 0.1 0.1 0.1 V/ns TCES2 2. Relative to SCK. CE# Active Setup Time 8 5 5 ns TCEH2 CE# Active Hold Time 8 5 5 ns TCHS2 CE# Not Active Setup Time 8 5 5 ns TCHH2 CE# Not Active Hold Time 8 5 5 ns TCPH CE# High Time 25 12.5 12 ns TCHZ CE# High to High-Z Output 19 12.5 12 ns TCLZ SCK Low to Low-Z Output 0 0 0 ns THLS HOLD# Low Setup Time 8 5 5 ns THHS HOLD# High Setup Time 8 5 5 ns THLH HOLD# Low Hold Time 8 5 5 ns THHH HOLD# High Hold Time 8 5 5 ns THZ HOLD# Low-to-High-Z Output 8 8 8 ns TLZ HOLD# High-to-Low-Z Output 8 8 8 ns TDS Data In Setup Time 3 3 3 ns TDH Data In Hold Time 4 4 4 ns TOH Output Hold from SCK Change 0 0 0 ns TV Output Valid from SCK 8/5 3 3. 30 pF/10 pF 8/5 3 8/5 3 ns THZ TLZ THHH THLS THHS 2005283 F104.0 HOLD# CE# SCK SO SI THLH |
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