©2012 Silicon Storage Technology, Inc.

DS25023B

06/13

7

1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash

SST39LF010 / SST39LF020 / SST39LF040

SST39VF010 / SST39VF020 / SST39VF040

Data Sheet

internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the com-

mand sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written

during the Chip-Erase operation will be ignored.

Write Operation Status Detection

The SST39LF010/020/040 and SST39VF010/020/040 devices provide two software means to detect

the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time.

The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-

Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or

Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with

either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software

routine should include a loop to read the accessed location an additional two (2) times. If both reads

are valid, then the device has completed the Write cycle, otherwise the rejection is valid.