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TPH8R808QM bảng dữ liệu(PDF) 2 Page - Toshiba Semiconductor |
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TPH8R808QM bảng dữ liệu(HTML) 2 Page - Toshiba Semiconductor |
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2 / 9 page ![]() TPH8R808QM 2 4. Absolute Maximum Ratings (Note) (Ta = 25 � unless otherwise specified) Characteristics Drain-source voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulsed) Power dissipation Power dissipation Power dissipation Single-pulse avalanche energy Single-pulse avalanche current Channel temperature Storage temperature (Tc = 25 �) (Silicon limit) (t = 100 µs) (Tc = 25 �) (Note 1) (Note 1), (Note 2) (Note 1) (Note 3) (Note 4) (Note 5) (Note 5) Symbol VDSS VGSS ID ID IDP PD PD PD EAS IAS Tch Tstg Rating 80 ±20 52 79 200 109 3 0.96 33 52 175 -55 to 175 Unit V A W mJ A � Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Note: This product is not designed for radiation resistance or cosmic ray resistance, and these natural environmentalfactors may affect reliability. In addition, radiation from the constituent materials of the product also becomes a natural environmental factor, which may affect reliability. 5. Thermal Characteristics Characteristics Channel-to-case thermal resistance Channel-to-ambient thermal resistance Channel-to-ambient thermal resistance (Tc = 25 �) (Ta = 25 �) (Ta = 25 �) (Note 3) (Note 4) Symbol Rth(ch-c) Rth(ch-a) Rth(ch-a) Max 1.37 50 156 Unit �/W Note 1: Ensure that the channel temperature does not exceed 175 �. Note 2: Limited by silicon chip capability. Note 3: Device mounted on a glass-epoxy board (a), Figure 5.1 Note 4: Device mounted on a glass-epoxy board (b), Figure 5.2 Note 5: VDD = 64 V, Tch = 25 � (initial), L =9.6 µH, IAS =52 A Fig. 5.1 Device Mounted on a Glass-Epoxy Board (a) Fig. 5.2 Device Mounted on a Glass-Epoxy Board (b) Note: This transistor is sensitive to electrostatic discharge and should be handled with care. 2022-09-28 Rev.2.0 ©2021-2022 Toshiba Electronic Devices & Storage Corporation |
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