công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

LCR1210-R100F bảng dữ liệu(PDF) 12 Page - Skyworks Solutions Inc.

tên linh kiện LCR1210-R100F
Giải thích chi tiết về linh kiện  SINGLE-CHIP DUAL PROSLIC®
PDF  59 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  SKYWORKS [Skyworks Solutions Inc.]
Trang chủ  http://www.skyworksinc.com
Logo SKYWORKS - Skyworks Solutions Inc.

LCR1210-R100F bảng dữ liệu(HTML) 12 Page - Skyworks Solutions Inc.

Back Button LCR1210-R100F Datasheet HTML 8Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 9Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 10Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 11Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 12Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 13Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 14Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 15Page - Skyworks Solutions Inc. LCR1210-R100F Datasheet HTML 16Page - Skyworks Solutions Inc. Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 59 page
background image
Si32260/1
12
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
Rev. 1.4 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • October 7, 2021
Table 9. Switching Characteristics—PCM Highway Interface1
Parameter
Symbol
Test
Condition
Min2
Typ2
Max2
Unit
PCLK Period
tp
122
1953
ns
PCLK Jitter Tolerance
tjitter
8nsRMS
Valid PCLK Inputs3
512
768
1.024
1.536
1.544
2.048
4.096
8.192
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
FSYNC Period4
tfs
—125
µs
PCLK Duty Cycle Tolerance
tdty
40
50
60
%
FSYNC Jitter Tolerance5
tjitter
±120
ns
Rise Time, PCLK
tr
25
ns
Fall Time, PCLK
tf
25
ns
Delay Time, PCLK Rise to DTX Active
td1
20
ns
Delay Time, PCLK Rise to DTX
Transition
td2
20
ns
Delay Time, PCLK Rise to DTX Tri-
state6
td3
20
ns
Setup Time, FSYNC to PCLK Fall
tsu1
25
ns
Hold Time, FSYNC to PCLK Fall
th1
20
ns
Setup Time, DRX to PCLK Fall
tsu2
25
ns
Hold Time, DRX to PCLK Fall
th2
20
ns
FSYNC Pulse Width
twfs
tp
125 µs–tp
Notes:
1. Characteristics for outputs specified with CL = 20 pF.
2. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4 V, VIL =0.4 V.
3. A constant PCLK and FSYNC are required.
4. FSYNC source is assumed to be 8 kHz under all operating conditions.
5. FSYNC Jitter Tolerance relative to PCLK.
6. Specification applies to PCLK fall to DTX tristate when that mode is selected.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59


bảng dữ liệu tải về

Go To PDF Page


Link URL



Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Liên kết đến bảng dữ liệu    |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com