LT8610AX datasheet(13/18 Pages) AD

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LTC2879X

Rev 0

For more information www.analog.com

Figure 10. The LTC2879X Balanced Signal Threshold

Voltages Preserve the Duty Cycle of an Incoming Signal.

The Differential Signal Received (Top) Has a Duty Cycle of

50%, and Is Reflected in the Receiver Output, RO (Bottom)

+200mV

–200mV

VTS+

VTS–

–120mV

+120mV

(A–B)

LTC2879X - BALANCED THRESHOLDS

2879X F10

APPLICATIONS INFORMATION

In contrast to this, some RS485 receivers have an unbal-

anced receiver threshold, used to address failsafe condi-

tions (see Failsafe Operation section). That is, the rising

and falling differential signal thresholds are both negative.

Figure 11 illustrates an example where the rising thresh-

old is –75mV and falling threshold is –120mV. This has

two disadvantages. First, the hysteresis is only 45mV in

this example, reducing the tolerance to noise, compared

to the 240mV of hysteresis in the LTC2879X. Secondly,

these unbalanced thresholds cause a duty cycle or pulse

width distortion at the receiver output relative to the input

signal. Figure 11 illustrates how a competitor part, using

the negative thresholds in this example introduces a duty

cycle distortion that becomes increasingly worse with low

input signal levels and slow input edge rates.

Figure 11. Typical Competitor Unbalanced Signal Threshold

Voltages Distort the Duty Cycle of an Incoming Signal. Input

Is 50% Duty Cycle (Top) but the Receiver Output Is Not 50%

Duty Cycle (Bottom)

+200mV

–200mV

VTS+

VTS–

–120mV

–75mV

(A–B)

UNBALANCED THRESHOLDS

2879X F11

Failsafe Operation

The LTC2879X has a failsafe feature that guarantees the

receiver output will be in a logic 1 state (the idle state)

when the inputs are shorted, left open, or terminated but

not driven for more than about 1.5µs. This failsafe feature

is guaranteed to work for inputs spanning the entire com-

mon mode range of –25V to +25V.

Failsafe operation is performed with a window compara-

tor to determine when the differential input voltage falls

between the rising and falling signal thresholds (VTS+,

and VTS–). If this condition persists for more than about

1.5µs then the receiver switches over to using the failsafe

thresholds (VTFS–, VTFS+), as illustrated in Figure 12 . The

delay allows normal data signals to transition through the

threshold region without being interpreted as a failsafe

condition, and thus maintaining the benefits of a balanced

threshold receiver.

SHUTDOWN MODE DELAY

The LTC2879X features a low power shutdown mode that

is entered when both the driver and receiver are simulta-

neously disabled (pin DE low and RE high). A shutdown

mode delay of approximately 250ns (not tested in pro-

duction) is imposed after the state is received before the

chip enters shutdown. If either DE goes high or RE goes

low during this delay, the delay timer is reset and the

chip does not enter shutdown. This reduces the chance

of accidentally entering shutdown if DE and RE are driven

in parallel by a slowly changing signal or if DE and RE are

Figure 12. The LTC2879X Signal Thresholds (VTS–, VTS+)

and Failsafe Thresholds (VTFS–, VTFS+)

(A–B)

2879X F12

–200mV

+200mV

–75mV

–120mV

+120mV

∆VTS

VTS–,VTFS– VTFS+

VTS+

∆VTFS

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