11 Layout

11.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends

placing a 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the

CRST pin, then minimize parasitic capacitance on this pin so the WDO delay time is not adversely affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a

0.1-µF ceramic capacitor as near as possible to the VDD pin.

• Place CCRST capacitor as close as possible to the CRST pin.

• Place CCWD capacitor as close as possible to the CWD pin.

• Place the pullup resistor on the WDO pin as close to the pin as possible.

11.2 Layout Example

Not to scale

VDD

WD-EN

SET1

GND

WDI

1

2

3

6

5

4

8

7

SET0

WDO

MR

TPS3435

Figure 11-1. Typical Layout for the TPS3435

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TPS3435

SNVSCF7 – DECEMBER 2022

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