INA232 datasheet(22/32 Pages) TI

22 / 32 page

Table 7-10. Mask/Enable Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

LEN (Alert Latch

Enable)

R/W

When the Alert Latch Enable bit is set to Transparent mode, the Alert pin and

Alert Function Flag (AFF) bit resets to the idle states when the fault condition has

been cleared.

When the Alert Latch Enable bit is set to Latch mode, the Alert pin and AFF bit

remains active following a fault until this register flag has been read.

This bit must be set to use the I2C Alert Response function.

0b = Transparent

1b = Latched Alert pin

Return to the Summary Table.

7.6.1.8 Alert Limit Register (Address = 7h) [reset = 0000h]

The alert limit register is shown in Table 7-11.

Table 7-11. Alert Limit Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

LIMIT

R/W

0000h

The Alert Limit Register contains the value used to compare to the

has been exceeded.

A two's complement value must be used for the Shunt Over Voltage

limit. Limit values entered should match the format of the targeted

Return to the Summary Table.

7.6.1.9 Manufacturer ID Register (Address = 3Eh) [reset = 5449h]

The manufacturer ID register is shown in Table 7-12.

Table 7-12. MANUFACTURE_ID Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

MANUFACTURE_ID

5449h

Reads back TI in ASCII

Return to the Summary Table.

INA232

SBOSAA2 – DECEMBER 2022

www.ti.com

Submit Document Feedback

Product Folder Links: INA232

INA232 bảng dữ liệu(PDF) 22 Page - Texas Instruments

INA232 bảng dữ liệu(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

bảng dữ liệu tải về

Link URL