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DRV8317S bảng dữ liệu(PDF) 41 Page - Texas Instruments

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8.6.4 SUP_STS Register (Offset = 5h) [Reset = 0000h]
SUP_STS is shown in Figure 8-31 and described in Table 8-14.
Return to the Table 8-9.
Figure 8-31. SUP_STS Register
15
14
13
12
11
10
9
8
PARITY
RESERVED
R-0h
R-0-0h
7
6
5
4
3
2
1
0
VMUV_WARN
VM_OV
RESERVED
CP_UV
RESERVED
RESERVED
VM_UV
RESERVED
R-0-0h
R-0-0h
R-0-0h
R-0h
R-0-0h
R-0h
R-0-0h
R-0h
Table 8-14. SUP_STS Register Field Descriptions
Bit
Field
Type
Reset
Description
15
PARITY
R
0h
Parity Bit if SPI_PEN is set to '1' otherwise reserved
14-8
RESERVED
R-0
0h
Reserved
7
VMUV_WARN
R-0
0h
VM under voltage warning fault status. This bit is not auto cleared
even when retry is enabled in VMUV_WARN_MODE. Can be
cleared by write to FLT_CLR or reset pulse on nSLEEP.
0h = No VM under voltage warning is detected
1h = VM under voltage warning is detected
6
VM_OV
R-0
0h
VM over voltage fault status. This bit is not auto cleared even when
retry is enabled in OVP_MODE. Can be cleared by write to FLT_CLR
or reset pulse on nSLEEP.
0h = No VM over voltage is detected
1h = VM over voltage is detected
5
RESERVED
R-0
0h
Reserved
4
CP_UV
R
0h
Charge pump under voltage fault status. This bit is not auto cleared
even when retry is enabled in UVP_MODE. Can be cleared by write
to FLT_CLR or reset pulse on nSLEEP.
0h = No charge pump under voltage is detected
1h = Charge pump under voltage is detected
3
RESERVED
R-0
0h
Reserved
2
RESERVED
R
0h
Reserved
1
VM_UV
R-0
0h
VM under voltage fault status. This bit is not auto cleared even when
retry is enabled in UVP_MODE. Can be cleared by write to FLT_CLR
or reset pulse on nSLEEP.
0h = No VM under voltage is detected
1h = VM under voltage is detected
0
RESERVED
R
0h
Reserved
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DRV8317
SLVSGT3 – DECEMBER 2022
Copyright © 2022 Texas Instruments Incorporated
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