Datasheet

10

Revision 1.02

19-08-2022

TLE4971

Datasheet

Fast Over-Current Detection (OCD) Output Parameters

Table 6 Common OCD Parameters

General conditions (unless otherwise specified): VDD = 3.3V; TS = -40°C … +125°C, CL=1nF.

Parameter

Symbol

Min

Typ

Max

Unit

Note / Test Conditions

Threshold level tolerance1)

ITHT

-10

-

10

%

Type tested

Response time jitter1)

ΔtD_OCD

-

-

0.25

µs

At 3σ, Irail=2xITHRx.x, input

rise time 0.1µs

Deglitch filter basic time

tOCDgl

400

500

600

ns

Detection minimum time

tOCD_low

3

-

-

µs

Valid for both OCDs

Load capacitance

tOCD_low

-

-

1

nF

Open-drain current

CL

-

-

1

mA

DC current

Pull-up resistor

RPU

1

4.7

10

kΩ

To VDD

1) Not subject to production test. Verified by design and characterization.

Table 7 OCD1 Parameters

Parameter

Symbol

Min

Typ

Max

Unit

Note / Test Conditions

Threshold level - Level11)2) 3)

ITHR1.1

-

1.25

-

x IFS

Factor with respect to IFS

(IFS = current full scale

according to programming

i.e. 120A)

Threshold level - Level21)2)

ITHR1.2

-

1.39

-

x IFS

Factor with respect to IFS

Threshold level - Level31)2)

ITHR1.3

-

1.54

-

x IFS

Factor with respect to IFS

Threshold level - Level41)2)

ITHR1.4

-

1.68

-

x IFS

Factor with respect to IFS

Threshold level - Level51)2)

ITHR1.5

-

1.82

-

x IFS

Factor with respect to IFS

Threshold level - Level61)2)

ITHR1.6

-

1.96

-

x IFS

Factor with respect to IFS

Threshold level - Level71)2)

ITHR1.7

-

2.11

-

x IFS

Factor with respect to IFS

Threshold level - Level81)2)

ITHR1.8

-

2.25

-

x IFS

Factor with respect to IFS

Response time4)

tD_OCD1

-

0.7

1

µs

IPN = 2*ITHR1.x

Fall time5)

tf_OCD1

-

100

150

ns

Deglitch filter setting2)6)

OCD1gl_mul

0

-

7

-

tdeglitch = OCD1gl_mul*tOCDgl

pre-configured setting = 0

1) Symmetric threshold level for positive and negative currents.

2) Can be programmed by user.

3) Pre-configured threshold level

4) Time between primary current exceeding current threshold and falling edge of OCD1-pin at 50%.

5) Not subject to production test. Verified by design and characterization.

6) The specified deglitching timing is valid when input current step overtakes the threshold of at least 10%.