AP64100Q

Document number: DS43575 Rev. 1 - 2

12 of 26

www.diodes.com

July 2021

© Diodes Incorporated

AP64100Q

Application Information (continued)

4

Electromagnetic Interference (EMI) Reduction with Ringing-Free Switching Node and Frequency Spread Spectrum (FSS)

In some applications, the system must meet EMI standards. In relation to high frequency radiation EMI noise

, the switching node’s (SW’s) ringing

amplitude is especially critical. To dampen high frequency radiated EMI noise, the AP64100Q device implements a proprietary, multi-level gate

driver scheme that achieves a ringing-free switching node without sacrificing the switching nod

e’s rise and fall slew rates as well as the converter’s

power efficiency.

To further improve EMI reduction, the AP64100Q device also implements FSS with a switching frequency jitter of ±6%. FSS reduces conducted

and radiated interference at a particular frequency by spreading the switching noise over a wider frequency band and by not allowing emitted

energy to stay in any one frequency for a significant period of time.

5

Adjusting Undervoltage Lockout (UVLO)

Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP64100Q device has a UVLO comparator that

monitors the input voltage and the internal bandgap reference. The AP64100Q disables if the input voltage falls below 3.1V. In this UVLO event,

both the high-side and low-side power MOSFETs turn off.

Some applications may desire higher VIN UVLO threshold voltages than is provided by the default setup. A 4µA hysteresis pull-up current source

on the EN pin along with an external resistive divider (R3 and R4) configures the VIN UVLO threshold voltages as shown in Figure 25.

VIN

R3

R4

ON

EN

1.18V

I1

1.5μA

I2

4μA

20kΩ

+

–

Figure 25. Adjusting UVLO

The resistive divider resistor values are calculated by:

������������ =

������. ������������������ ∙ ������������������ − ������������������������

������. ������������������������������

Eq. 2

������������ =

������. ������������ ∙ ������������

������������������������ − ������. ������������������ + ������. ������������������ ∙ ������������

Eq. 3

Where:



VON is the rising edge VIN voltage to enable the regulator and is greater than 3.7V



VOFF is the falling edge VIN voltage to disable the regulator and is greater than 3.3V

6

Output Overvoltage Protection (OVP)

The AP64100Q implements output OVP circuitry to minimize output voltage overshoots during decreasing load transients. The high-side power

MOSFET turns off, and the low-side power MOSFET turns on, when the feedback voltage exceeds 110% of the 0.8V internal reference voltage in

order to prevent the output voltage from continuing to increase.