SPEAR-07-NC03 datasheet(13/194 Pages) STMICROELECTRONICS

13 / 194 page

SPEAR-07-NC03

4 Pin Descriptions

13/194

Pin Descriptions

4.1

Functional Pin Groups

Note:

Note: symbol / means multiplexing modes

Table 1.

Pin Descriptions by Functional Groups

Group

Pin Name

Function

Remark

Clocks, Reset

and

configuration.

MCLKI

Oscillator Clock Input

25 MHz

MCLKO

Oscillator Clock Output

25 MHz

PowerGood

System Reset Input

nResetOut

Peripheral Chips Driving Reset Output

Synchronous with System

Clock

TMODE0

Test Mode Selector

“1”

→ Test

PCLK

Output Clock (25 MHz)

Memory

Interface

Add[22:11],

Add[10]/AP,

Add[9:0]

Address Bus

Add[10]/AP is the auto pre-charge control

pin. The auto pre-charge command is

issued at the same time as burst read or

burst write by asserting high on Add[10]/

ROM Banks: 16MB Max.

DRAM Banks: 32MB Max.

Data[15:0]

External, Bi-directional, 16 bit Data Bus

nRAS[3:0]/

nSDCS[3:0]

Row Address Strobe for EDO DRAM/

nSDCS is chip select pin for SDRAM

nSDRAS

Row Address Strobe for SDRAM

nSDCAS

Column Address Strobe for SDRAM

SDCLK

System Clock for SDRAM

48 MHz

CKE

Clock enable signal for SDRAM

nWE

Write Enable for external devices.

nECS[1:0]

Chip Select for external I/O Bank

Banks size: 16KB

nRCS[1:0]

Not ROM/SRAM/FLASH Chip Select

nOE

Not Output Enable for memory I/O

nCAS[1:0]/ DQM[1:0]

nCAS is the Column Address Strobe for

EDO DQM is data mask signal for

SDRAM.

SPEAR-07-NC03 bảng dữ liệu(PDF) 13 Page - STMicroelectronics

SPEAR-07-NC03 bảng dữ liệu(HTML) 13 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL