PI6C182

Precision 1-10 Clock Buffer

6

PS8165D

07/19/04

PCB Layout Suggestion

Note:

1. This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout.

2. As a general rule, C1-C7 should be placed as close as possible to their respective VDD.

3. Recommended capacitor values:

C1-C7 = 0.1μF, ceramic

C8 = 22μF

C5

C6

C1

C7

C2

C3

C4

Ferrite Bead

VCC

C8

22uF

Via to GND Plane

Via to VDD Plane

Void in Power Plane

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VDD

VSS

VDD

VSS

VSS

VDD

VDD

VDD

VSS

VDD

VSS

VSS

VDD

VSS

Figure 2. Design Guidelines

SDRAM

RS

10

CL

PI6C182

SDRAM

DIMM

Spec.

Clock from

Chipset