ICS95V860 datasheet(6/10 Pages) ICST

6 / 10 page

ICS95V860

0675D—01/07/04

Notes:

Refers to transition on noninverting output in PLL bypass mode.

While the pulse skew is almost constant over frequency, the duty cycle error

increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where

the cycle (tc) decreases as the frequency goes up.

Timing Requirements

TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

Input clock frequency

freqop

100

225

MHz

Input clock duty cycle

dtin

CLK stabilization

TSTAB

µs

Switching Characteristics

TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Low-to high level

propagation delay time

tPLH

CLK_IN to any output

5.5

High-to low level propagation

delay time

tPLL

CLK_IN to any output

5.5

Output enable time

tEN

PD# to any output

Output disable time

tdis

PD# to any output

Period jitter

Tjit (per)

-75

Half-period jitter

t(jit_hper)

-70

Input clock slew rate

tsl(i)

V/ns

Output clock slew rate

tsl(o)

12.5

V/ns

Cycle to Cycle Jitter

Tcyc-Tcyc

-75

Static phase offset

tspo

-75

Output to Output Skew

Tskew

Duty cycle

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