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HV7151SP bảng dữ liệu(PDF) 49 Page - Hynix Semiconductor |
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HV7151SP bảng dữ liệu(HTML) 49 Page - Hynix Semiconductor |
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49 / 89 page ![]() HV7151SP CMOS Image Sensor Confidential With Image Signal Processing This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 49 - 2003 Hynix Semiconductor Inc. AWB Mode Control 2 [AEMODE2 : 71h : 02h] 7 6 5 4 3 2 1 0 Reserved AWB Low Speed AWB Sub- sampling mode AWB Analog Gain Control Reserved 0 0 0 0 0 0 1 0 AWB Low Speed With this bit set to high, analog gain speed is decreased to 1/4 of the normal speed. AWB Sub-sampling Mode AWB statistics is executed on 1/4 of original image data to save power consumption AWB Analog Gain Control AWB updates R/B gain registers(14h,16h) in order to reach optimum white balance state Cb Frame Mean Value [CBTRGT : 73h : 80h] 7 6 5 4 3 2 1 0 Cb Frame Mean 1 0 0 0 0 0 0 0 This register defines Cb target frame mean value for AWB operation. Cr Frame Mean Value [CRTRGT : 74h : 80h] 7 6 5 4 3 2 1 0 Cr Frame Mean 1 0 0 0 0 0 0 0 This register defines Cr target frame mean value for AWB operation. AWB Lock Boundary [AWBLBND : 75h : 02h] 7 6 5 4 3 2 1 0 Reserved AWB Lock Boundary 0 0 0 0 0 0 1 0 It specifies Cb/Cr frame mean values’ displacement from Cb/Cr Target (73h-74h) value where AWB |
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