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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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MAX2 bảng dữ liệu(PDF) 39 Page - Altera Corporation |
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MAX2 bảng dữ liệu(HTML) 39 Page - Altera Corporation |
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39 / 297 page  Chapter 2: MAX II Architecture 2–17 Global Signals © October 2008 Altera Corporation MAX II Device Handbook The global clock network drives to individual LAB column signals, LAB column clocks [3..0], that span an entire LAB column from the top to the bottom of the device. Unused global clocks or control signals in a LAB column are turned off at the LAB column clock buffers shown in Figure 2–14. The LAB column clocks [3..0] are multiplexed down to two LAB clock signals and one LAB clear signal. Other control signal types route from the global clock network into the LAB local interconnect. See “LAB Control Signals” on page 2–5 for more information. Figure 2–13. Global Clock Generation Note to Figure 2–13 : (1) Any I/O pin can use a MultiTrack interconnect to route as a logic array-generated global clock signal. 4 4 GCLK0 Global Clock Network GCLK1 GCLK2 GCLK3 Logic Array(1) |
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