7.6.1.4 BRDCAST Register (offset = 6h) [reset = 0000h when RSTSEL is logic low, or reset = 8000h when

RSTSEL is logic high]

Figure 7-7. BRDCAST Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

BRDCAST-DATA [15:0]

W-0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high

Table 7-6. BRDCAST Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

BRDCAST-DATA [15:0]

W

0000h when

RSTSEL is

logic low

or

8000h when

RSTSEL is

logic high

Writing to the BRDCAST register forces the DAC channels that

are set to broadcast from the SYNC register to update the active

register data to the BRDCAST-DATA bits.

7.6.1.5 DAC-n Register (offset = 8h–9h) [reset = 0000h when RSTSEL is logic low, or reset = 8000h when

RSTSEL is logic high]

Figure 7-8. DAC-n Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DAC-n-DATA [15:0]

W-0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high

Table 7-7. DAC-A Data Register Field Descriptions (8h)

Bit

Field

Type

Reset

Description

15-0

DAC-A-DATA [15:0]

W

0000h when

RSTSEL is

logic low

or

8000h when

RSTSEL is

logic high

Data are MSB aligned in straight binary format.

Table 7-8. DAC-B Data Register Field Descriptions (9h)

Bit

Field

Type

Reset

Description

15-0

DAC-B-DATA [15:0]

W

0000h when

RSTSEL is

logic low

or

8000h when

RSTSEL is

logic high

Data are MSB aligned in straight binary format.

DAC82002

SBASAK1A – AUGUST 2022 – REVISED DECEMBER 2022

www.ti.com

18

Submit Document Feedback

Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DAC82002