9.2.1.1 Design Requirements

9.2.1.1.1 Enable, Disable, and Reference Voltage Guidelines

As shown in Figure 9-1, the A1 and A2 channels have a maximum output voltage equal to Vref_A, and the B1

and B2 channels have a maximum output voltage equal to Vpu when Vref_B is connected through a 200-kΩ

resistor to a 3.3-V Vpu power supply and Vref_A is set 1.8 V.

The LSF0108-Q1 has an EN input that is used to disable the device by setting EN LOW, which places all I/Os

in the high-impedance state. The power consumption is very low because LSF0108-Q1 is a switch-type voltage

translator. It is recommended to always enable LSF0108-Q1 for bidirectional application (I2C, SMBus, PMBus, or

MDIO).

Table 9-2. Application Operating Condition

PARAMETER

MIN

TYP

MAX

UNIT

Vref_A(1)

reference voltage (A)

0.95

4.5

V

Vref_B

reference voltage (B)

Vref_A + 0.8

5.5

V

VI(EN)

input voltage on EN pin

Vref_A + 0.8

5.5

V

Vpu

pull-up supply voltage

0

Vref_B

V

(1)

Vref_A have to be the lowest voltage level across all of inputs and outputs.

Note

The 200 kΩ, pull-up resistor is required to allow Vref_B to regulate the EN input.

A filter capacitor on Vref_B is recommended. Also Vref_B and VI(EN) are recommended to be at 1.0 V higher

than Vref_A for best signal integrity.

9.2.1.1.2 Bias Circuitry

For proper operation, VCCA must always be at least 0.8 V less than VCCB (VCCA + 0.8

≦ VCCB). The 200 kΩ

pull-up resistor is required to allow Vref_B to regulate the EN input and properly bias the device for translation.

A 0.1 µF capacitor is recommended for providing a path from Vref_B to ground for high frequency noise. Vref_B

and VI (EN) are recommended to be 1.0 V higher than Vref_A for best signal integrity.

Attempting to drive the EN pin directly with a push-pull output device is a very common design error with the

LSF01 series of devices. It is also very important to note that current does flow into the A-side voltage supply

during normal operation. Not all voltage sources can sink current, so be sure that applicable designs can handle

this current. For more design details, see the Understanding the Bias Circuit for the LSF Family video.

1.8 V

Vref_A

VCCB

EN

200 k

Vref_B

3.3 V

A1

B1

0.1 mF

Figure 9-2. Bias Circuitry Inside the LSF0108-Q1 Devices

LSF0108-Q1

SDLS967E – MAY 2016 – REVISED NOVEMBER 2022

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