MFS5600AMBA0ES datasheet(56/111 Pages) NXP

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NXP Semiconductors

FS5600

Automotive buck regulator and controller with voltage monitors and watchdog timer

The mirror registers modified in this fashion take effect during power-up when

VDDOTP_GPIO < 1 V. Contact your NXP representative for commands needed to

access the mirror registers.

17.13.5 INIT_RUN

The INIT_RUN state is entered after the power-up state. Either or both SW1 and SW2

may be enabled to enter the INIT_RUN state. The state machine can remain in the

INIT_RUN state indefinitely. In this state, the state machine waits for conditions to

transition to the normal state if enabled to do so. Alternatively, the state machine may

proceed to power down to the Deep Fail-Safe state if conditions enabling this are met.

INIT_RUN state may also be entered from the normal state by setting the

GOTO_INIT_RUN and clearing the NOT_GOTO_INIT_RUN bits.

17.13.6 Normal state

In the normal state, the FS0B pin is de-asserted to indicate to the system that essential

parameters monitored by the FS5600 are in expected range. The normal state is

entered from the INIT_RUN state, provided conditions for this transition are met.

OTP_NORMAL_STATE_EN bit should be set to 1 to enable transition to the normal state.

OTP_ERRMON1_SAFE = 1 is an enabling condition for a valid ERRMON1 signal

to control transition to the normal state. OTP_ERRMON2_SAFE = 1 is an enabling

condition for a valid ERRMON2 signal to control transition to the normal state.

OTP_PGOOD1_SAFE = 1 is an enabling condition for a valid PGOOD1 output to control

transition to the normal state. OTP_PGOOD2_SAFE = 1 is an enabling condition for a

valid PGOOD2 output to control transition to the normal state.

See Section 17.13.10 for conditions to transition to the normal state.

17.13.7 Deep fail-safe state

In the deep fail-safe state, the FS5600 is shut down. All the regulators are turned off and

signal outputs are asserted low. The only way to exit deep fail-safe state is through a

power cycle on the VIN input, or if both EN1 and EN2 are pulled low in the application.

Deep fail-safe can be entered when the fault error counter reaches is maximum value, or

when a watchdog failure is programmed to go to deep fail-safe. OTP_DFS_EN must be

set to 1 to enable transition to the Deep Fail-Safe state. See Section 17.13.10 for detailed

conditions.

17.13.8 Power-down

The FS56 enters a graceful power-down when both EN1 and EN2 are asserted low in the

application.

The power-down follows a reverse of the power-up sequence for the GPOs (each

following the OTP_GPOx_DELAY[2:0] setting) followed by SW1 and/or SW2.

If entering power-down from deep fail-safe, thermal shut-down, or power-up, the state

machine immediately enters shut-down mode after SW1, SW2, and GPIOs are asserted

low (no power-down sequence).

FS5600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 2 August 2022

56 / 111

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