ADC14155EB datasheet(4/19 Pages) NSC

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Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

IN−

Differential analog input pins. The differential full-scale input

signal level is two times the reference voltage with each input

pin signal centered on a common mode voltage, V

CM.

IN+

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very

close to the pin to minimize stray inductance. A 0.1 µF

capacitor should be placed between V

RP and VRN as close to

the pins as possible, and a 10 µF capacitor should be placed

in parallel.

RP and VRN should not be loaded. VRM may be loaded to

1mA for use as a temperature stable 1.5V reference.

It is recommended to use V

RM to provide the common mode

voltage, V

CM, for the differential analog inputs, VIN+ and VIN−.

REF

This pin can be used as either the +1.0V internal reference

voltage output (internal reference operation) or as the external

reference voltage input (external reference operation).

To use the internal reference, V

REF should be decoupled to

AGND with a 0.1 µF, low equivalent series inductance (ESL)

capacitor. In this mode, V

REF defaults as the output for the

internal 1.0V reference.

To use an external reference, overdrive this pin with a low

noise external reference voltage. The output impedance of the

internal reference at this pin is 9k

Ω. Therefore, to overdrive this

pin, the impedance of the external reference source should be

<< 9k

Ω.

This pin should not be used to source or sink current.

The full scale differential input voltage range is2*V

REF.

DIGITAL I/O

CLK+

The clock input pins can be configured to accept either a

single-ended or a differential clock input signal.

When the single-ended clock mode is selected through

CLK_SEL/DF (pin 8), connect the clock input signal to the

CLK+ pin and connect the CLK− pin to AGND.

When the differential clock mode is selected through

CLK_SEL/DF (pin 8), connect the positive and negative clock

inputs to the CLK+ and CLK− pins, respectively.

The analog input is sampled on the falling edge of the clock

input.

CLK−

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