Figure 25. Buck-boost PCB layout (top)

Figure 26. Buck-boost PCB layout (bottom)

The transfer function of the power section for buck-boost topology is summarized below:

GLC(s)=G0⋅ 1+ SωZ ⋅ 1− SωRHPZ

1+ SωLC⋅Q+ S2ωLC2

(36)

with below singularities and parameters:

ωZ= 1C0⋅RES;ωRHPZ=R0⋅(1−D)2

D⋅L ;ωLC= 1−DL⋅C0

(37)

D= V0V0+VIN;Q= 1−D⋅R0⋅ C0L;G0= V0D⋅(1−D)

(38)

The singularity ωRHPZ = 2π * fRHPZ, computed at the maximum load and minimum input voltage, is the limitation

in the loop bandwidth design. Typically the maximum bandwidth, fBW, is designed to be lower than one fourth of

the above described singularity, in order to achieve a good phase margin.

In case ωZ and ωLC are lower than the target bandwidth, a type II compensation network is enough for loop

stabilization, following the compensation strategy described in Section 6.4.1 Type II compensation network . In

case ceramic or very low ESR electrolytic output capacitors are used, ωZ is typically higher than the target fBW so

a type III compensation network is necessary, as described in Section 6.4.2 Type III compensation network.

8.2

Negative buck-boost

The A7987 device can implement the step-up/down conversion with a negative output voltage.

Figure 27. Negative buck-boost schematic example shows the schematic to regulate -24 V and about 0.6 A

maximum load, assuming VIN falling in the range from 18 V to 36 V. No further external components are added to

the standard buck topology.

A7987

Negative buck-boost

DS12928 - Rev 3

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